JPH0754350B2 - Moving target image integrator - Google Patents

Description

The present invention relates to an apparatus for integrating a target signal in an image.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional device,
In the figure, (1) is an arithmetic unit that performs weighted addition of two sets of video signals, (2) is a frame memory for storing the arithmetic unit output and applying it again to the arithmetic unit input, (3)
Is a frame timing generator for generating an address of the frame memory (2), (4a) is an X address counter for counting the X-direction address of the frame memory (2), (4b) is a frame memory (2) Y address counter for counting Y direction address of (9a), (9b)
Are signals for resetting the X and Y address counters (4a) and (4b) respectively, and (10a) and (10b) are the X and Y address counters (4
These are the clocks in a) and (4b).

Next, the operation will be described. Original video signal f _N (I, J)
Is input to one input terminal of the arithmetic unit (1), weighted addition is performed inside the arithmetic unit (1) with the video signal g _N-1 (I, J) from the frame memory (2), and the output g _N (I, J)
Is obtained. The relationship between g _N (I, J) and f _N (I, J) and g _N-1 (I, J) shown in Fig. 2 is usually used. Further, here, I and J represent the addresses in the X and Y directions of the screen, which means that the calculation is performed between the corresponding pixels of the screen, and N and (N-1) are the Nth address respectively. The frame is a subscript representing the (N-1) th frame.
The address of the frame memory (2) is driven by the X reset (9a), X clock (10a) and the Y reset (9b), Y clock (10b) from the frame timing generator (3). It is controlled by a counter (4a) and a Y address counter (4b).

[Problems to be solved by the invention]

Since the conventional device is configured as described above, if the target is stationary at the same coordinate point (I, J), the signals of the (N-1) th frame and the Nth frame are associated with each other. However, when the target is moving, it is only possible to add the points of the jagged edges, and the integration effect drops.

The present invention has been made to solve the above problems, and an object thereof is to obtain an integral effect with respect to a moving target.

[Means for Solving Problems] An image integrator according to the present invention reads an address of a frame memory, which is an input signal of an arithmetic unit, at a value according to a target speed, and performs arithmetic between pixels of the arithmetic unit. In this case, the goals overlap.

[Action]

In the present invention, the frame memory is stored at the same address position as the original video signal when the arithmetic unit output signal is written, but at the time of reading, the signal is read from the offset X, Y address position according to the target speed. Read out.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, in which (1) to (4) have the same functions as those of the conventional device. (5) is the target relative speed detector,
(6a) and (6b) are X and Y adder / subtractors, respectively.
The outputs of the X and Y address counters (4a) and (4b) and the target relative speed detector (5) are added and subtracted. (7a),
(7b) are the memory input and memory output selectors, respectively.

In the image integrator configured as described above, the relative speed with respect to the target is detected by the target relative speed detector (5) as V
As ELO (X), VELO (Y), each direction component of X and Y is detected, and this value is used to display on-screen address corresponding to the magnitude of target X-direction relative speed and target Y-direction relative speed. The converted values K and L are calculated and subtracted from the outputs I and J of the X address counter (4a) and the Y address counter (4b) by the X adder / subtractor (6a) and the Y adder / subtractor (6b).
By obtaining J-L and accessing the first and second frame memories (2a) and (2b), the target position g _N-1 (I-K, J-K) of the image of the (N-1) -th frame is obtained. ) Is applied to the other input of the computing unit (1), f _N (I, J) is applied as one input, and the output for each corresponding point with the matching target position is g _N (I, J).
Can be obtained as

In the example shown in FIG. 1, the frame memories A, B and 2
It was configured so that there would be no conflict between writing and reading.

As mentioned above, Then, the moving target signal can be integrated.

Also, based on the frame start signal (11) created by the frame timing generator (3), the memory output selector (7a), the memory input selector (7b), the X selector (8a), the Y selector (8b). ) Are switched alternately in synchronization, and in one combination, X switching is performed so that the address (I-K, J-K) of the second frame memory B (2b) is selected. Bowl (8
a) and Y switch (8b) are connected, and the output of the second frame memory B (2b) is taken out from the memory output switch (7a). Further, the X switch (8a) and the Y switch (8b) are connected so that the address (I, J) of the first frame memory A (2a) is selected, and the first frame memory A (2a) is connected. ) Is written to the input through the memory input selector (7b). In the other remaining combination, the above operation is performed with the frame memory A and the frame memory B interchanged.

Thus, assuming that the switches (7a), (7b), (8a), and (8b) are in the solid line state in the (N-1) th frame, the switching is performed in the dotted line state in the Nth frame.

Through these, the two frame memories are written and read in parallel, the independence for the memory is secured, and the signal processing algorithm is continuously executed while retaining the old data and the new data.

In the above embodiment, only a single moving target is described, but it is obvious that the circuits can be provided in parallel so that the integration can be performed for moving targets having a plurality of speeds.

〔The invention's effect〕

As described above, according to the present invention, since the reading of the frame memory is configured to be accessed by the address to which the offset corresponding to the target moving speed is applied, the integration of the moving target image, which is difficult with the conventional device, is performed. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image integrating device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional device. In the figure, (1) is an arithmetic unit, (2) is a frame memory, (3) is a frame timing generator, (4a) is an X address counter, (4b) is a Y address counter, and (5).
Is a target relative speed detector, (6a) is an X adder / subtractor, (6b) is a Y adder / subtractor, (7a) is a memory output selector,
(7b) is a memory input selector, (8a) is an X selector, (8b)
Is a Y switch, (9a) is an X reset, (9b) is a Y reset, (10a) is an X clock, (10b) is a Y clock, (1
1) is a frame start signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display part H04N 7/18 G

Claims (1)

[Claims] 1. An arithmetic unit for performing weighted addition of an input image signal and a stored image signal, first and second frame memories for storing an output of the arithmetic unit, and an output of the arithmetic unit for the first A memory input switch for switching and inputting to the frame memory and the second frame memory, and a memory output switching for switching the outputs of the first and second frame memories and inputting to one input end of the arithmetic unit And X, Y address counter that creates X, Y addresses I, J from the clock, and X, Y of the relative speed of the target
A target relative speed detector that detects a directional component and generates converted values K and L of the X and Y directional components to the on-screen address, and the X address I of the X address counter are subtracted by the converted value K I- An X adder / subtractor for obtaining K, a Y adder / subtractor for subtracting the Y address J of the Y address counter by the conversion value L to obtain JL, the X, Y address counter, X, Y adder / subtractor, and the first, Between the second frame memory, the address (I, J) or (I-K, J-L) of the first frame memory is selected, and the address of the second frame memory ( I-K, J-
L) is provided with an X, Y switcher connected so as to select (I, L), and a frame timing generator for creating timings and clocks necessary for the above respective switchers and counters. Moving target image integrator.