JPH0754386B2 - Display device - Google Patents
Display deviceInfo
- Publication number
- JPH0754386B2 JPH0754386B2 JP61035668A JP3566886A JPH0754386B2 JP H0754386 B2 JPH0754386 B2 JP H0754386B2 JP 61035668 A JP61035668 A JP 61035668A JP 3566886 A JP3566886 A JP 3566886A JP H0754386 B2 JPH0754386 B2 JP H0754386B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- display device
- source
- film
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、薄膜トランジスタアレイを用いた表示装置
において、大面積化および高解像度化を行う際の配線の
低抵抗化および断線不良の低減の向上を期するようにし
た表示装置に関するものである。Description: TECHNICAL FIELD The present invention relates to a display device using a thin film transistor array, which is capable of improving the resistance of wiring and the reduction of disconnection defects when increasing the area and increasing the resolution. The present invention relates to a display device designed to meet the requirements.
上記の表示装置は通常２枚の対向基板の間に液晶あるい
はエレクトロクロミツク（以下、ECという）材料などの
表示媒体を挟み、この表示媒体に電圧を印加する方法で
構成される。The above-mentioned display device is usually constructed by sandwiching a display medium such as a liquid crystal or an electrochromic (hereinafter referred to as EC) material between two opposing substrates and applying a voltage to the display medium.
この際、少なくとも一方の基板にマトリクス状に配列し
た画素電極を設け、これらの画素を選択的に動作するた
めに各画素毎にFET（電界効果トランジスタ）およびダ
イオードなどの非線形スイツチング素子を設けている。At this time, pixel electrodes arranged in a matrix are provided on at least one substrate, and a non-linear switching element such as a FET (field effect transistor) and a diode is provided for each pixel in order to selectively operate these pixels. .
従来、この種の表示装置を構成する薄膜トランジスタア
レイは第３図および第４図に示すようなものがあつた。
第３図は従来法により形成した薄膜トランジスタアレイ
の部分平面図、第４図は第３図のＡ−Ａ部の断面図であ
る。Conventionally, the thin film transistor array forming this type of display device has been shown in FIGS. 3 and 4.
FIG. 3 is a partial plan view of a thin film transistor array formed by a conventional method, and FIG. 4 is a sectional view taken along the line AA of FIG.
この第３図、第４図の両図において、１は透明絶縁性基
板、２は遮光膜、３はパツシベーシヨン膜である。この
パツシベーシヨン膜３上にソース電極配線４とドレイン
・画素電極５が形成されている。In both FIGS. 3 and 4, 1 is a transparent insulating substrate, 2 is a light shielding film, and 3 is a passivation film. The source electrode wiring 4 and the drain / pixel electrode 5 are formed on the passivation film 3.
また、パツシベーシヨン膜３上に半導体膜６が形成され
ており、その上に順次ゲート絶縁膜７、ゲート電極８が
形成されている。A semiconductor film 6 is formed on the passivation film 3, and a gate insulating film 7 and a gate electrode 8 are sequentially formed on the semiconductor film 6.
液晶表示装置などのように透過型のデイスプレイを形成
する際、ソース電極・配線４およびドレイン・画素電極
５はITO（Indium Tin Oxide）のような透明導電膜で同
時形成する方法があるが、その上層に形成される半導体
層などを、ソース電極およびドレイン電極の段差部分で
切らずに形成するためには、ソース電極およびドレイン
電極のITOの膜厚は薄い方がよく、通常1000Å位であつ
た。When forming a transmissive display such as a liquid crystal display device, there is a method of simultaneously forming a source electrode / wiring 4 and a drain / pixel electrode 5 with a transparent conductive film such as ITO (Indium Tin Oxide). In order to form the upper semiconductor layer without cutting at the step of the source and drain electrodes, the ITO film of the source and drain electrodes should be thin, usually around 1000Å. .
したがつて、表示面積が大きくなり、しかも高解像度な
デイスプレイを形成する際、ソース電極配線の抵抗が高
くなる。たとえば、ソース配線を長さ10cmで巾30μｍに
形成した場合の抵抗は100KΩ以上となり、ここに信号を
入力した場合信号の減衰が大きく、さらにその抵抗と入
力容量（たとえば50pF以上）との積である時定数は10μ
sec以上となり、高周波動作が困難となる。また、1000
Å程度の膜厚では断線が多発し、表示上不利となるとい
つた欠点があつた。Therefore, the display area becomes large and the resistance of the source electrode wiring becomes high when a high-resolution display is formed. For example, if the source wiring is 10 cm long and 30 μm wide, the resistance will be 100 KΩ or more, and if a signal is input here, the signal will be greatly attenuated. Some time constant is 10μ
It becomes more than sec and high frequency operation becomes difficult. Also 1000
At a film thickness of about Å, wire breakage frequently occurred, which was disadvantageous in terms of display.
この発明は、かかる問題点を解決するためになされたも
ので、工程をほとんど増さずにソース配線の低抵抗化を
行い、さらに断線不良を低減でき、かつ表示品質の高い
表示装置を得ることを目的とする。The present invention has been made in order to solve such a problem, and to reduce the resistance of the source wiring without increasing the number of steps, to further reduce disconnection defects, and to obtain a display device with high display quality. With the goal.
この発明に係る表示装置は、遮光膜形成と同時に第２の
ソース配線を形成し、第２のソース配線が第１のソース
電極配線に電気的に並列に接続されて、第１のソース電
極配線とともに２層のソース配線を形成したものであ
る。In the display device according to the present invention, the second source wiring is formed at the same time when the light-shielding film is formed, and the second source wiring is electrically connected in parallel to the first source electrode wiring. In addition, two layers of source wiring are formed.
この発明においては、ソース配線が２層配線となること
からソース配線抵抗を低減化でき、時定数が小さくな
り、高速動作を行う。In the present invention, since the source wiring is a two-layer wiring, the source wiring resistance can be reduced, the time constant can be reduced, and high speed operation can be performed.
以下、この発明の表示装置の実施例について図面に基づ
き説明する。第１図はその一実施例の薄膜トランジスタ
アレイで形成した平面図であり、第２図は第１図のＢ−
Ｂ線の断面図である。この第１図および第２図におい
て、第３図および第４図と同一部分には同一符号を付し
て説明する。An embodiment of a display device of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the thin film transistor array according to the embodiment, and FIG.
It is sectional drawing of a B line. In FIG. 1 and FIG. 2, the same parts as those in FIG. 3 and FIG.
この第１図、第２図において、９は第２のソース配線、
10はコンタクトホール、11はコンタクト膜であり、この
部分がこの発明によつて新たに付加された部分である。In FIGS. 1 and 2, 9 is the second source wiring,
10 is a contact hole, 11 is a contact film, and this portion is a portion newly added according to the present invention.
以下にこの発明の具体的な構成の製造工程を述べる。ま
ずガラスなどの透明で高絶縁性の基板１を鏡面研磨しそ
の表面を洗浄する。The manufacturing process of the specific constitution of the present invention will be described below. First, a transparent and highly insulating substrate 1 such as glass is mirror-polished and its surface is washed.
次に、Alなどの低抵抗な金属、金属化合物あるいは金属
合金を真空蒸着法などで堆積する。この後ホトリソグラ
フイなどの方法で、アイランド状の遮光膜２と同時にラ
イン状の第２のソース配線９を形成する。Next, a low resistance metal such as Al, a metal compound or a metal alloy is deposited by a vacuum deposition method or the like. Thereafter, a line-shaped second source wiring 9 is formed simultaneously with the island-shaped light-shielding film 2 by a method such as photolithography.
次に、パツシベーシヨン層３として、Si3N4やSiO2など
の透明絶縁膜をCVD法などで堆積する。Next, as the passivation layer 3, a transparent insulating film such as Si 3 N 4 or SiO 2 is deposited by the CVD method or the like.
次に、ソース電極・配線４およびドレイン・画素電極５
をITOなどの透明導電膜を用いて形成し、さらにａ−Si,
p−Si,CdSeなどの半導体層６およびSi3N4,SiO2,Al2O3な
どの絶縁膜でゲート絶縁膜７を形成する。Next, the source electrode / wiring 4 and the drain / pixel electrode 5
Is formed using a transparent conductive film such as ITO, and a-Si,
The gate insulating film 7 is formed of a semiconductor layer 6 of p-Si, CdSe or the like and an insulating film of Si 3 N 4 , SiO 2 , Al 2 O 3 or the like.
ここで、ソース電極・配線４およびパツシベーシヨン膜
３に透明導電膜で形成されたソース電極配線４と遮光膜
２の形成と同時に形成された第２のソース配線９を接続
するためのコンタクトホール10を形成する。そして、最
後にAlなどの金属、金属化合物あるいは金属合金でゲー
ト電極８を形成する。Here, a contact hole 10 for connecting the source electrode / wiring 4 and the source electrode wiring 4 formed of a transparent conductive film to the passivation film 3 and the second source wiring 9 formed simultaneously with the formation of the light shielding film 2 is formed. Form. Finally, the gate electrode 8 is formed of a metal such as Al, a metal compound or a metal alloy.
このとき、同時に透明電極で形成されたソース電極・配
線４と遮光膜２の形成と同時形成した第２のソース配線
９を接続するコンタクト膜11を形成する。At this time, a contact film 11 for connecting the source electrode / wiring 4 formed of a transparent electrode and the second source wiring 9 formed simultaneously with the formation of the light shielding film 2 is formed at the same time.
なお、このときゲート配線と本来のソース配線の層間絶
縁は半導体層とゲート絶縁膜７がそれを兼ねている。At this time, the semiconductor layer and the gate insulating film 7 also serve as interlayer insulation between the gate wiring and the original source wiring.
このようにして形成された薄膜トランジスタアレイ基板
と他の透明電極およびカラーフイルタなどを有する基板
との間に所定の間隔を保持し、これらの２枚の基板間に
液晶やEC材料などの表示媒体を挿入して、表示装置が完
成する。The thin film transistor array substrate thus formed and a substrate having other transparent electrodes and color filters are kept at a predetermined distance, and a display medium such as liquid crystal or EC material is placed between these two substrates. The display device is completed by inserting.
上記構成の薄膜トランジスタアレイおよび表示装置はソ
ース電極配線４が金属、金属化合物あるいは金属合金と
透明導電膜の２層で形成されているため、低抵抗化が可
能であり、たとえば、第２のソース配線９にAlを用いた
とき、ソース配線の長さが10cmで巾20μｍで厚さ3000Å
の場合の抵抗は1KΩ以下となり、ITO単独の場合より２
桁以上低くすることができる。したがつて、抵抗損失に
よる信号の減衰がない。In the thin film transistor array and the display device having the above-described configurations, the source electrode wiring 4 is formed of two layers of a metal, a metal compound or a metal alloy, and a transparent conductive film, so that the resistance can be reduced. For example, the second source wiring When Al is used for 9, the length of the source wiring is 10 cm, the width is 20 μm, and the thickness is 3000 Å
In the case of, the resistance is 1 KΩ or less, which is 2 compared with the case of ITO alone.
It can be lowered by several digits. Therefore, there is no signal attenuation due to resistance loss.
また、その抵抗と入力容量の積である時定数も小さくな
り、特に上記のようにAlを用いた場合には時定数は２桁
以上小さくなり、高周波での動作が可能となる。Also, the time constant, which is the product of the resistance and the input capacitance, becomes small, and particularly when Al is used as described above, the time constant becomes smaller by two digits or more, and high-frequency operation becomes possible.
さらに、断線に対しても冗長性があり、第２のソース配
線９と透明導電膜で形成された本来のソース配線４のい
ずれか一方が断線しても、もう一方で導通を保持でき
る。そして、この両者が同じ場所で断線する確率は極め
て小さいので、断線不良はほとんど皆無となる。Further, there is redundancy against disconnection, and even if one of the second source line 9 and the original source line 4 formed of the transparent conductive film is disconnected, the other side can maintain electrical continuity. Since the probability that both of them will be disconnected at the same place is extremely small, there is almost no disconnection defect.
また、このようなソースの２層配線を行つても、工程と
しては従来のものよりパツシベーシヨン膜３にコンタク
トホール10を形成する工程が一つ増すだけである。Further, even if such two-layer wiring of the source is performed, the number of steps for forming the contact hole 10 in the passivation film 3 is increased by one as compared with the conventional method.
したがつて、この発明を用いて大面積で高解像度の表示
装置を形成すれば簡単な工程で極めて表示品質の高い表
示装置が得られる。Therefore, if a large-area, high-resolution display device is formed by using the present invention, a display device of extremely high display quality can be obtained by a simple process.
この発明は以上説明したとおり、本来のソース配線以外
に第２のソース配線を遮光膜と同時に形成して本来のソ
ース配線との２層配線とするようにしたので、工程をほ
とんど増さずにソース配線の低抵抗化とそれにともない
動作の高速化ができ、また回路として冗長性を持たせた
ので断線不良を低減でき、これにともない、表示品質の
高い表示装置が得られる効果を奏する。As described above, according to the present invention, in addition to the original source wiring, the second source wiring is formed at the same time as the light-shielding film to form the two-layer wiring with the original source wiring. The resistance of the source wiring can be reduced and the operation can be speeded up accordingly, and since the circuit has redundancy, disconnection defects can be reduced, and accordingly, a display device with high display quality can be obtained.
第１図はこの発明の表示装置の一実施例を構成する薄膜
トランジスタアレイの部分平面図、第２図は第１図のＢ
−Ｂ線の断面図、第３図は従来の表示装置を構成する薄
膜トランジスタアレイの部分平面図、第４図は第３図の
Ａ−Ａ線の断面図である。 １……基板、２……遮光膜、３……パツシベーシヨン
膜、４……ソース電極配線、５……ドレイン・画素電
極、６……半導体膜、７……ゲート絶縁膜、８……ゲー
ト電極、９……第２のソース配線、10……コンタクトホ
ール、11……コンタクト膜。 なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a partial plan view of a thin film transistor array which constitutes an embodiment of the display device of the present invention, and FIG. 2 is a portion B of FIG.
-B is a cross-sectional view, FIG. 3 is a partial plan view of a thin film transistor array that constitutes a conventional display device, and FIG. 4 is a cross-sectional view taken along the line AA of FIG. 1 ... Substrate, 2 ... Shading film, 3 ... Passivation film, 4 ... Source electrode wiring, 5 ... Drain / pixel electrode, 6 ... Semiconductor film, 7 ... Gate insulating film, 8 ... Gate electrode , 9 ... second source wiring, 10 ... contact hole, 11 ... contact film. The same reference numerals in the drawings indicate the same or corresponding parts.
Claims (2)
たはエレクトロクロミック材料などの表示材料を有する
表示装置であって、一方の対向電極が透明絶縁性の基板
上に下層から遮光膜、パッシベーション層、ソース電極
配線とドレイン画素電極、半導体膜、ゲート絶縁膜、最
上層にゲート電極を有して層状をなす薄膜トランジスタ
アレイの基板を備えた表示装置において、上記透明絶縁
性の基板上に上記遮光膜と同時に形成された第２のソー
ス配線が上記ソース電極配線と電気的に並列に接続され
て上記ソース電極配線とともに２層のソース配線を形成
することを特徴とする表示装置。1. A display device comprising two counter electrodes and a display material such as a liquid crystal or an electrochromic material sandwiched between the counter electrodes, wherein one counter electrode is a transparent insulating substrate from the lower layer to a light-shielding film, In a display device comprising a substrate of a thin film transistor array having a passivation layer, a source electrode wiring and a drain pixel electrode, a semiconductor film, a gate insulating film, and a gate electrode in the uppermost layer, the transparent insulating substrate having the above-mentioned structure. A display device, wherein a second source wiring formed at the same time as the light-shielding film is electrically connected in parallel with the source electrode wiring to form a two-layer source wiring together with the source electrode wiring.
ョン層にあけたコンタクトホールを通して上記ソース電
極配線と接続されていることを特徴とする特許請求の範
囲第１項記載の表示装置。2. The display device according to claim 1, wherein the second source wiring is connected to the source electrode wiring through a contact hole formed in the passivation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035668A JPH0754386B2 (en) | 1986-02-19 | 1986-02-19 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035668A JPH0754386B2 (en) | 1986-02-19 | 1986-02-19 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62192783A JPS62192783A (en) | 1987-08-24 |
| JPH0754386B2 true JPH0754386B2 (en) | 1995-06-07 |
Family
ID=12448253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61035668A Expired - Lifetime JPH0754386B2 (en) | 1986-02-19 | 1986-02-19 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0754386B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2652786B2 (en) * | 1987-05-08 | 1997-09-10 | 株式会社日立製作所 | Liquid crystal display |
| JP2755376B2 (en) * | 1994-06-03 | 1998-05-20 | 株式会社フロンテック | Manufacturing method of electro-optical element |
| KR100873497B1 (en) * | 2002-10-17 | 2008-12-15 | 삼성전자주식회사 | Integrated LCD with Fingerprint Recognition Device and Manufacturing Method Thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57120992A (en) * | 1981-01-21 | 1982-07-28 | Seiko Instr & Electronics | Picture display device |
| JPS599636A (en) * | 1982-07-07 | 1984-01-19 | Seiko Epson Corp | Liquid crystal display body |
| JPS5959266A (en) * | 1982-09-28 | 1984-04-05 | Nippon Paint Co Ltd | Method for inhibiting formation of dripping mark in spray-type surface treatment of coil |
-
1986
- 1986-02-19 JP JP61035668A patent/JPH0754386B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62192783A (en) | 1987-08-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |