JPH0754473B2 - Inter-CPU communication instruction execution method on virtual machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] As an instruction for performing communication between CPUs in a computer system having a plurality of CPUs, for example, there is a SIGP instruction.
The SIGP instruction normally transfers information from the CPU that has executed the SIGP instruction on the hardware to the other CPU.

Therefore, since it is impossible to execute the SIGP instruction on the logical CPU of the virtual computer, when performing computer-to-computer communication with the virtual computer, the control is handed over to the system control program that summarizes each virtual computer. Emulation was performed by the system control program.

Therefore, the system control program always intervenes in the communication between the CPUs on the virtual machine, and there is a problem that the processing efficiency of the system decreases.

In order to solve such a conventional problem, the present invention provides a table storing pending (pending) information for each domain, and by operating this pending information, a SIGP instruction or the like on the logical CPU of the virtual machine It discloses a technique capable of directly executing an instruction related to communication between CPUs.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of communication between CPUs in a virtual computer system, and in particular, an instruction for performing communication between CPUs (hereinafter also referred to as SIGP instruction) does not go through a system control program. This relates to a control method that can be directly executed by the CPU of the virtual machine.

[Prior Art] In a virtual computer system that has a plurality of independent virtual computers and is configured to execute processing by assigning at least one set of real computers to each virtual computer whenever necessary, Each has an operating system (OS), but there is a system control program that controls each virtual machine as a whole.

In such a virtual computer system, communication between logical CPUs on each virtual computer is indispensable for executing processing.

Normally, each CPU operates asynchronously, so communication between CPUs is performed by the source CPU
When U requests an interrupt (equivalent to a general external interrupt), the CPU that receives it holds this information, and at the next timing when this can be executed, the pending interrupt is pruned and This is performed under the control of performing processing related to the interrupt.

Therefore, it is impossible for the logical CPU of the virtual machine to directly perform such inter-CPU communication processing. Therefore, conventionally, in order to realize the communication between the CPUs on the virtual computer, the emulation was performed by interposing the system control program described above. For example, Sanya and Akiyama. Virtual computer. May 20, 1980 (4th edition of the first edition). Kyoritsu Shuppan Co., Ltd. p167-175 proposes a communication method using a virtual machine communication function (VMCF). This provides a parameter list on the main memory and an external interrupt for VMCF as a communication means. And when enabling VMCF,
First, notify the control program (CP) that VMCF will be used.

[Problems to be Solved by the Invention] As described above, in the conventional inter-CPU communication on the virtual machine, the system control program intervenes every time the logical CPU executes the SIGP instruction, and It adopted a method of performing processing related to interrupts on a computer.
Therefore, the communication between the CPUs has a problem in that the control becomes complicated and the processing steps become large compared with the normal processing executed in the OS of the virtual machine, and the processing efficiency of the entire system is reduced.

In view of such conventional problems, an object of the present invention is to provide a control method capable of directly performing communication between CPUs by a SIGP instruction on a virtual computer without depending on a system control program. .

[Means for Solving the Problems] According to the present invention, the above object is achieved by the means described in the claims.

That is, according to the present invention, a storage area that can be accessed from each logical CPU in a domain is associated with each of the logical CPUs in the domain, and one of the logical CPUs in the domain executes instructions related to inter-CPU communication. When a request is executed, a table is displayed to display pending information that can identify the request content of the instruction and the logical CPU that executed the instruction, and the storage area accessible from each logical CPU in the domain When any of the logical CPUs in the domain executes an instruction related to inter-CPU communication in association with each of the logical CPUs of the domain, the request content by the instruction and the logical CPU that executed the instruction can be distinguished from each other. A table for displaying information is provided, and when the logical CPU is dispatched, the contents of the table are loaded into the pending latch of the hardware of the real CPU and CPU San machine
When executing an instruction related to inter-communication, a means for performing a display operation according to the hold information of the communication destination logical CPU on the table and a hold of the area given to itself on the table It is an inter-CPU communication instruction execution method on a virtual machine provided with a means for referring to information and performing processing according to the state.

[Embodiment] FIG. 1 is a diagram for explaining an embodiment of the present invention, in which 1 is a pending table for controlling a SIGP instruction provided on a memory, 2 and 3 are registers in a CPU, and 4 is a CPU. Is shown.

In this embodiment, the SI used in the virtual machine
Of the GP commands, a particularly frequent sense (hereinafter also referred to as S).
In addition, S is also described in the figure. ), External call (hereinafter also referred to as EC, and EC
3), and an emergency signal (hereinafter, also referred to as ES, also referred to as ES in the figure), the case where the requests are directly executed on the virtual computer.

In addition, this embodiment supports 16 domains 0 to 15 and 8 logical CPUs 0 to 7 for each domain, as is clear from the contents of the pending table 1. Each logical CPU is
For ES and EC, 1 bit is associated with each of the 3 source CPUs to provide pending information. This pending table 1 is placed in a fixed area on the main memory that can be accessed by any logical CPU.

Now, it is assumed that the logical CPU2 of the domain 1 targets the CPU3 and executes the SIGP instruction whose order is EC. The starting point address of the pending table 1 is fixed.

The half-word address to be accessed can be obtained from the own domain ID and the target logical CPU address.

In this case, the starting point address is + 1 × 16 + 3 × 2.

By accessing this halfword, the target CPU
Get pending information for. And if either
If there is EC pending from the CPU, set the condition code and status there and end the SIGP instruction. If all EC pendings are "0", the bit corresponding to the own CPU is set to "1" and the condition code = 0. The pending information on this table is loaded to the real CPU when the logical CPU is dispatched. Then, the EC or ES pending is notified to the hardware interrupt control circuit. Therefore, it is possible to issue a SIGP instruction to a logical CPU that does not exist in the system when the SIGP instruction is executed.

The logical CPU that has received the pending by SIGP on the virtual machine also operates the pending information of this table at the time of interrupt processing.

In this example, when the logical CPU # 3 of the domain # 1 is dispatched, the corresponding halfword is loaded and the logical CP
You can see the EC pending from U # 2. When an external interrupt is generated by this, the bit corresponding to the EC pending from CPU # 2 on the table is turned off.

As described above, the SIGP instruction can be directly executed on the virtual computer, but the hardware for executing on the real computer can be utilized to further improve the responsiveness.

SIGP on a real computer sends an order only to the target CPU, but SIGP on a virtual computer sends an order to all CPUs in the system.

At this time, the domain ID of the target CPU and the logical CPU address are sent together with the flag that indicates SIGP on the virtual machine, and the receiving side checks it and SIGP for the own CPU
Determine whether or not. According to the above example, if the logical CPU # 3 of the domain # 1 is running on any of the real CPUs in the system, the CPU of the 3 performs SIGP reception and the EC external interrupt request is issued. Stands. This allows an immediate interrupt to occur without waiting for the pending table to load.

[Effect of the Invention] As described above, according to the present invention, in a virtual computer system, when a virtual computer executes a SIGP instruction, it is possible to directly communicate between CPUs without going through a system control program.

At that time, the logical CPU of the corresponding virtual machine is the real CPU.
If you are driving in
There is also an advantage that processing related to the SIGP instruction can be performed by hardware processing.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention. 1 ... Pending table, 2, 3 ... Register, 4
……CPU

Claims (2)

[Claims] 1. In a virtual computer system having a plurality of CPUs, a storage area that can be accessed from each logical CPU in a domain is associated with each of the logical CPUs in the domain, and either When a logical CPU executes an instruction related to inter-CPU communication, a table is provided for displaying pending information capable of identifying the content requested by the instruction and the logical CPU that executed the instruction. When dispatching the logical CPU, the table is displayed. Contents are loaded into the pending latch of the hardware of the real CPU, and when executing instructions related to inter-CPU communication on the virtual machine, the communication destination logic on the table
A means for referring to the CPU hold information and performing a display operation according to the state, and a means for performing a process according to the state by referring to the hold information in the area given to itself on the table. CP on the virtual machine characterized by the provision
Inter-U communication instruction execution method. 2. When the virtual computer executes an instruction related to inter-CPU communication, the hardware issues an inter-computer communication call to all CPUs in the system. Inter-CPU communication instruction execution method on virtual machine.