JPH0754634B2 - EPROM integrated circuit device - Google Patents

Description

The present invention relates to an EPROM integrated circuit device.

(Prior Art) A read-only memory composed of a semiconductor integrated circuit capable of erasing stored contents that have been electrically written by applying a high voltage or irradiating with an ultraviolet ray and re-storing new contents can be provided. Commercialized, EP such a memory device
It is called ROM. This EPROM is composed of a normal memory cell, an address decoder, a write control circuit and a sense amplifier, and has a plurality of address terminals, a plurality of data input / output terminals, a power supply terminal for normal operation, and a high voltage for writing. It has a power supply terminal, a program terminal, and a standby terminal. Therefore, the four states of the EPROM in the write state, the standby state, the verify state at the time of writing, and the read state are determined by the combination of inputs of the high power supply terminal, the program terminal, the standby terminal, etc. A standby terminal that keeps power consumption in a standby state at all times and a normal operation state only during reading is provided independently.

(Problems to be Solved by the Invention) However, when the integration density is improved with the progress of the semiconductor integration technology to increase the number of memory elements, for example, when the number of elements can be doubled, the connection terminal The number of address pins will be increased by one, but it is often difficult to increase the number of address pins by standardizing the element outline. Especially in EPROMs that require a large number of states, we want to minimize the number of state setting pins. There is a problem called.

An object of the present invention is to solve the above problems and to provide an EPROM integrated circuit device which can obtain the above-mentioned four states only by the combination of inputs of a high power supply terminal and a write control input terminal.

(Means for Solving Problems) The present invention relates to a write voltage detection circuit that determines that a write voltage is applied when an input voltage from a high voltage power supply terminal exceeds a certain value, and the write voltage detection circuit. A state control circuit that determines four states of a write state, a standby state, a verify state, and a read state based on a combination of the output of the voltage detection circuit and the input from the write control input terminal is configured. Outputs indicating four states from this state control circuit are applied to an address decoder, a write control circuit, a sense amplifier, etc. to create a necessary state.

(Example) Hereinafter, the Example of this invention is described in detail with reference to drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a write voltage detection circuit (hereinafter VDET) 1 and a state control circuit (hereinafter STSC) 2
, EPROM element circuit (hereinafter MCEL) 3, address decoder circuit (hereinafter ADDEC) 4, sense amplifier circuit (hereinafter SEN)
S) 5 and a write control circuit (WCTR) 6 and has a high power supply terminal V _pp connected to VDET1, a write control input terminal WCT connected to STSC2, and a plurality of address inputs. It has a terminal ADDIN, a plurality of data input / output terminals DAIO, a power supply terminal V _cc and a ground terminal GND.

To explain the functional circuit and signal transmission / reception in FIG. 1 below, the power supply terminal V _cc and the ground terminal GND are connected to the respective functional circuits described above to supply a voltage for normal operation of, for example, + 5V. ing. VDET1 receives + 5V from the high power supply terminal V _pp , which is normally the same voltage as that applied to the power supply terminal Vcc, but when a high voltage, for example + 21V, is applied, STSC2
The detection signal is sent to the detection signal line VH connected to. On the other hand, STSC2 is composed of a decoder circuit, for example, "0" is always output from the above detection signal line VH, "1" is output as a detection signal, and "0" or "1" is input to the write control input line. Is given, the outputs shown in Table 1 are obtained at the traffic signals W, VF and STB corresponding to the write state, the verify state and the standby state.

Therefore, when the "1" signal is applied to the WCTR6 from the output terminal W, the WCTR6 applies the write voltage to the ADDEC4 via the signal line WR, decodes the input address signal, and writes it to the MCEL3. Address signal is given and SE is sent via signal line SB.
Stops reading operation and sends a signal to NS5, and data input / output terminal D
The write data given to AIO is taken in and writing is performed using the high voltage + 21V given to MCEL3. When a "1" signal is given to WCTR6 from output terminal VF, WCTR6 is the same as when writing to signal line WR, but no stop signal is sent to signal line SB, and data input / output terminal Without writing DA-IO, read the written address and send the data. In addition, the "1" signal from the output terminal STB is SENS5
When applied to SENS5, SENS5 turns off the power of the internal circuit that consumes a lot of power and creates a standby state. Furthermore, in the 4th state of Table 1, STSC2 does not output an output signal in particular, but in this case, ADDEC4, MCEL3 and SENS5 supply voltage +5
When V is given and an address input is given, a normal read output is obtained from the input / output terminal DAIO.

The combination of signals of the detection signal line VH and the write control input line does not necessarily have to be as shown in Table 1, and it can be arbitrarily assigned to four states.

(Effects of the Invention) As described in detail above, according to the present invention, the four states required for the EPROM can be obtained by the two inputs of the high voltage input for writing and the write control input. There is an effect that it is not necessary to provide a standby terminal that is provided, and the memory capacity can be increased with the same number of terminals as the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 1 ... Write voltage detection circuit (VDET), 2 ... State control circuit (STSC), 3 ... EPROM element circuit (MCEL), 4 ... Address decoder circuit (ADDEC), 5 ... Sense amplifier circuit (SENS) ), 6 ... Write control circuit (WCTR).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsuji Kimura 5-33-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (56) Reference JP-A-58-32297 (JP, A)

Claims (1)

[Claims] 1. A high voltage power supply terminal, a power supply terminal to which a predetermined power supply voltage is applied during operation, a ground terminal, a write control input terminal,
A write voltage detection circuit having a plurality of address input terminals and a data input output terminal, further connected to the high voltage terminal and detecting whether or not a high voltage for writing is applied to the high voltage power supply terminal; A state control circuit connected to a write control input terminal and receiving the detection output of the write voltage detection circuit, wherein the state control circuit outputs the detection output to the high voltage power supply terminal to the high voltage for writing. Is applied, a write state or a verify state is created according to the logic level of the write control input terminal, and the detection output applies the write voltage to the high voltage power supply terminal. If the predetermined power supply voltage is applied, the EPRO is characterized by creating a standby state or a continuous state according to the logic level of the write control input terminal. M integrated circuit device.