JPH0810555B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates to an integrated circuit using the ^{I 2 L (I ntegrated I njection} L ogic), in particular designability, ARM highly scalable
It related to the peripheral circuit of the (R andom A ccess M emory) .

[Conventional technology]

Conventionally, built-in I ² L in analog digital coexistence LSI
RAM is discussed in a paper entitled "High Voltage Analog Circuit Coexistence 256 Bit I ² L RAM" by Kaneko et al. In IEICE Transactions Vol. J66-C No. 9.

FIG. 2 shows a connection diagram of a conventional bit driver and a memory cell. This figure shows 1 word = 8 bits
4 shows the case where the X address is 1 bit and the X address control line is two. In this figure, when the X address control line X1 is at "L" level and X2 is at "H" level, the bit driver BD
(1,1) to BD (8,1) are selected and memory cell MC (1,1)
~ Writing to MC (8,1) is performed. On the contrary, when the X address control line X1 is at "H" level and X2 is at "L" level, the bit drivers BD (1,2) to BD (8,2) are selected and MC (1,2) are selected.
2) to MC (8,2) are written. In the case of the configuration shown in this figure, the number of input side signal lines of the bit driver is
There are two X address control lines, one read / write control line, and eight data input lines for a total of 11 lines.

Next, a specific circuit of the conventional bit driver will be described.

FIG. 3 is a diagram showing a specific circuit of BD (1,1) and BD (1,2) in FIG. The inside of the broken line is 1 bit for the bit driver. This bit driver uses npn transistors Q ₂₅ , Q ₂₆ , Q ₂₇ , Q ₂₈ that drive the bit lines and pnp transistors Q ₂₁ , Q that supply the base current to these npn transistors during writing.
_{Has 22} , Q ₂₃ , Q ₂₄ .

The I ² L gates G _{21 to} G ₂₈ are connected to the input signals X1, X2, R / W, Din.
It takes the logic 1～Din8, on the Q ₂₅ to Q _28, has a function of controlling the off. In the circuit of this conventional example, the address control line X1
The base of I ² L gate G ₂₅ is connected to
A total of the same number of gates as one word, that is, eight gates of input terminals are connected to X1. Further, the input terminal of the I ² L8 gate is similarly connected to the address signal line X2.

All bit drivers are connected to the read / write signal line R / W, and the base for 16 gates is connected. When the same signal is input to a plurality of gates as described above, if the number of gates increases, current hopping may occur due to variations in gate characteristics, which may cause malfunction.

Due to this current hopping, malfunction tends to occur as the number of gates connected to the same signal line increases. Therefore, the bit driver of this conventional example may cause a malfunction when the scale of the memory increases. For example, 1 word = 8
If the X address is 2 bits, the number of bit drivers becomes 32, and the base of the I ² L32 gate is connected to the read / write signal line R / W, which increases the possibility of malfunction. Therefore, the conventional bit driver has a limit in increasing the scale.

[Problems to be solved by the invention]

The above-mentioned conventional circuit is used when the scale and configuration of the memory are changed.
There was a problem that the current hogging of the I ² L gate was not taken into consideration and the memory scale and configuration could not be changed freely.

It is an object of the present invention to provide a highly integrated circuit in a bit driver for I ² L RAM in which malfunction due to current hopping is eliminated and the number of elements is reduced.

[Means for solving problems]

The above objects are achieved by a circuit for inputting signals to the plurality of I ² L gate from the same signal line, the I ² L gate the CGI (control ground inverter;-controled ground in
verter) Realized by replacing the gate.

That is, a semiconductor device that achieves the above object includes a plurality of memory cells (MC), a plurality of bit line pairs (B11, / B11 (/ represents an inverted signal)) to which the plurality of memory cells are connected, A plurality of bit driver circuits (BD) provided corresponding to a plurality of bit line pairs for writing data to the selected memory cell, and a signal connected to the bit driver circuit and writing to the selected memory cell And an X address control line (X1 ') which is connected to the bit driver circuit and supplies an X address control signal which is a signal obtained by taking the logic of the X address signal and the read / write signal. ) And the bit driver circuit includes a pair of bit line driving transistors (Q15, Q16) each having a collector electrode connected to each of the bit line pairs and the bit line driving transistor. A pair of base current supply transistors (Q11, Q12), which supplies a base current to the base electrode of the line driving transistor whose collector electrode is connected, and an input signal supplied to the input signal line, A signal corresponding to the signal and its inverted signal are connected to the IIL gate circuits (G11, G12) for supplying the base electrodes of the pair of bit line driving transistors and the X address control line, according to the X address control signal. A gate circuit (G15) for controlling current supply to the base electrode of the bit line driving transistor, the gate circuit comprising a pnp transistor (Q55) having the X address control line connected to its base electrode. ) And the pnp
An npn transistor (Q56) in which the emitter electrode is connected to the base electrode of the transistor, the base electrode is connected to the collector electrode of the pnp transistor, and the collector electrode is connected to the base electrode of the bit line driving transistor. It is configured to include.

[Action]

The above-described semiconductor device has a bit driver circuit controlled by the X address control signal, and when writing is instructed by the X address control signal (high level), it is supplied to the input signal line (Din1). The input signal thus generated is supplied as a complementary signal to the base electrodes of the bit line driving transistors (Q15, Q16) via the IIL gate circuits (G11, G12). At this time, the high-level X address control signal is supplied to the base electrode of the pnp transistor (Q55) and the emitter electrode of the npn transistor (Q56) that form the CGI gate, so that its output becomes a high impedance state. Therefore, bit line drive transistors (Q15, Q16)
The base electrode of the memory cell is connected to the output of the IIL gate circuit (G11, G12) so that one is at high level and the other is at low level. The signal corresponding to the input signal is written to (MC).

On the other hand, at the time of reading etc., X is applied to the base electrode of the pnp transistor (Q55) and the emitter electrode of the npn transistor (Q56).
CG is supplied with the low-level signal used as the address control signal.
The output of the I gate goes low and the IIL gate circuit (G1
The base electrodes of the bit line driving transistors (Q15, Q16) are set to a low level regardless of the output of (1, G12), and writing is prohibited by a signal from the input signal line (Din1).

According to the present invention, by having the above-mentioned means,
The bit driver circuit is controlled to write to and prohibit writing to memory cells, and by using a CGI gate (a gate that uses the ground terminal of the I ² L gate as one of the signal input terminals) When the same signal is input, even if this ground terminal is connected to the same signal line, current hooking does not occur and malfunction does not occur.

〔Example〕

FIG. 4 shows a connection diagram of the bit driver and the memory cell according to the present invention. The structure of FIG. 4 shows the case of the same cell structure as the structure of the conventional example shown in FIG. Fourth
The difference between the illustrated embodiment and the conventional example is that the X address signal X Addres
This is the method of inputting s and the read / write signal R / W. In this embodiment, the logical sum of the inverted signal XAddress of the X address signal and the read / write signal R / W is input to the X addresses X1 'and X2'. For this reason, in this embodiment, the read / write signal line R / W is not required as an input signal of the bit driver.
The number of wires can be reduced.

FIG. 1 shows a circuit of an embodiment of a bit driver according to the present invention. In the figure, the inside of the broken line is 1 bit for the bit driver. Bit driver of this embodiment, the npn transistor _{Q 15, Q 16, Q 17} , Q 18 to drive the bit lines during writing, this
It has pnp transistors Q ₁₁ , Q ₁₂ , Q ₁₃ , and Q ₁₄ which supply a base current to the npn transistor. Further, G ₁₁ , ~ G ₁₆ take the logic of the input signals X'1, X2 'and Din 1 ~ Din 8, and Q ₁₅ , Q ₁₆ , and
Q ₁₇ , Q ₁₈ ON / OFF control.

The circuit of this embodiment is different from the conventional circuit in that X
The point is that CGI gates G ₁₅ and G ₁₆ are used as gates for receiving the logical sum signals X1 ′ and X2 ′ of Address and R / W. In this, conventionally, those that required I ² L4 gates and circuits having the same function in I ² L2 gate CGI1 gate total 3 gate bits driver 1bit content was reduced number of elements. In addition, by using the CGI gate as an input, the current hopping of the signal input section gate is prevented, the memory cell size and configuration are changed, and the circuit does not malfunction even if the number of gates connected to the same signal line increases. .

 Next, the operation of the CGI gate will be described.

FIG. 5 (a) is an equivalent circuit diagram of a normal I ² L gate and shows the I ² L gates G ₂₅ and G ₂₇ of FIG. The normal I ² L gate shown in FIG. 5 (a) is an inverted npn transistor.
The Q _52, Q _54, on a base as an input terminal, a circuit to turn off. On the other hand, the CGI gate shown in FIG. 5 (b) uses the emitters of the reverse npn transistors Q ₅₆ and Q ₅₈ as input terminals, and turns on and off Q ₅₆ and Q _58. Even if a large number of gates are connected, there is a feature that current hopping does not occur. Also, this CGI gate is connected to Q ₅₅ , when the reverse npn transistors Q ₅₆ and Q ₅₈ are off.
Since Q ₅₇ is also turned off during non-operation is a low power consumption circuit without consuming power.

〔The invention's effect〕

According to the present invention, current hopping does not occur even if signals are input to a large number of gates from the same signal line. Thank you
Even if the scale and configuration of the I ² L RAM change, the peripheral circuits can be prevented from malfunctioning.

Further, the number of gates of the bit driver can be reduced and the number of input signal lines can be reduced by using an X address signal and a signal obtained by taking the logic of the read / write signal as the input signal of the bit driver.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a connection between a conventional bit driver and a memory cell, FIG. 3 is a circuit diagram of a conventional bit driver, and FIG. 4 is a diagram of the present invention. FIG. 5A is an equivalent circuit diagram of a normal I ² L gate, and FIG. 5B is an equivalent circuit diagram of a CGI gate. B11, B11, B12, B12 …… bit line, Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ …… pn
p-transistor, Q ₁₅ , Q ₁₆ , Q ₁₇ , Q ₁₈ ...... npn transistor, G ₁₁ ,, G ₁₂ , G ₁₃ , G ₁₄ ...... I ² L gate, Q ₁₅ , Q ₁₆ ...... CGI gate, X Address + R / W …… X1 ', X2', Din1, D, which is the logical sum of the inverted signal of the X address signal and the read / write signal
in8 …… Bit driver input signal, V _CC , V _BB …… Power supply line, MC (1,1), MC (8,1), MC (1,2), MC (8,2) …… Memory cell , BD (1,1), BD (8,1), BD (1,2), BD (8,2)
…… Bit driver, X Address, X1, X2 …… X address control signal, R / W …… Read / write signal, Din1, Din8 ……
Data input signal, Q ₂₁ , Q ₂₂ , Q ₂₃ , Q ₂₄ ...... pnp transistor, Q ₂₅ , Q ₂₆ , Q ₂₇ , Q ₂₈ ...... npn transistor, G ₂₁ , G ₂₂ , G
₂₃ , G ₂₄ , G ₂₅ , G ₂₆ , G ₂₇ , G ₂₈ ...... I ² L gate, BDC (1,1), BD
C (8,1), BDC (1,2), BDC (8,2) ... bit driver,
INJ …… Injector line, Q ₅₁ , Q ₅₃ , Q ₅₅ , Q ₅₇・ ・ ・ pnp transistor, Q ₅₂ , Q ₅₄ , Q ₅₆ , Q ₅₈ ...... npn transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Hayashi 1448, Kamisuihonmachi, Kodaira-shi, Tokyo In-house Hitachi Ultra ELS Engineering Co., Ltd. 280 In Hitachi Central Research Laboratory, Ltd. (72) Inventor Makoto Furu, 111 Nishiyokote-cho, Takasaki-shi, Gunma Inside Takasaki Plant, Hitachi, Ltd.

Claims (1)

[Claims] 1. A plurality of memory cells, a plurality of bit line pairs to which the plurality of memory cells are connected, and data writing to a selected memory cell provided corresponding to the plurality of bit line pairs. A plurality of bit driver circuits to perform, an input signal line connected to the bit driver circuit and supplying a signal to be written to the selected memory cell, and an X address signal and a read / write signal connected to the bit driver circuit. And an X address control line that supplies an X address control signal that is a signal obtained by taking the logic of the above. The bit driver circuit includes a pair of bit line driving circuits, each collector electrode of which is connected to each of the bit line pairs. Transistor and a pair of bases for supplying a base current to the base electrode of the bit line driving transistor whose collector electrode is connected. Current supply transistor and an IIL gate circuit which receives an input signal supplied to the input signal line and supplies a signal corresponding to the input signal and its inverted signal to the base electrodes of the pair of bit line driving transistors. And a gate circuit connected to the X address control line and controlling current supply to the base electrode of the bit line driving transistor according to the X address control signal, wherein the gate circuit is the X address control line. Is connected to its base electrode by pn
A p-transistor, its emitter electrode is connected to the base electrode of the pnp transistor, its base electrode is connected to the collector electrode of the pnp transistor, and its collector electrode is connected to the base electrodes of the pair of bit line driving transistors. Np
A semiconductor device comprising an n-transistor.