JPH0754896B2 - Digital delay circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital delay circuit, and more particularly to a digital delay circuit suitable for obtaining a delay with a wide delay range and high speed and high accuracy.

[Conventional technology]

The conventional device, as described in Japanese Patent Laid-Open No. 61-75615, generates N frequency-divided outputs in which the phase of the input time reference signal input in the time period T is sequentially shifted by T in the period NT. Means for receiving one of the N frequency-divided output signals, N counters having a maximum count time NT for setting a delay amount as a counter input value at the timing of the signal, and the N counters. It is composed of a logical sum circuit for obtaining the logical sum of the carry signals, and obtains a variable delay width from O to NT with respect to the time period T of the input time reference signal.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider variations in the propagation delay time from the clocks of the N counters to the carry signal C _0, and causes variations in the propagation delay times of the N counters in the output time reference signal. However, there is a problem in that jitter occurs. Further, since the clock is directly input to the preset counter, no consideration is given to the clock frequency, and the delay resolution is limited by the upper limit of the operating frequency of the counter.

The object of the present invention is to provide a wide delay range and a high delay resolution,
An object of the present invention is to provide a digital delay circuit that can obtain a delay output without jitter.

[Means for solving problems]

The purpose is to receive an input signal and obtain N of the period T of the input signal.
Means for generating N frequency-divided outputs whose double cycle is shifted by T, N prescaler means for frequency-dividing the clock in response to each frequency-divided output signal, and N for counting each frequency-divided clock
By providing a number of counters, an OR gate that ORs the counting end signals of these N counters, and means for delaying the output signal of the OR gate with the resolution of the clock cycle,
To be achieved.

[Action]

The input signal is divided by N and then input to the prescaler that divides the clock, and the division start point of each prescaler is controlled. Each counter counts the frequency-divided clock whose frequency division start point is controlled, and outputs a count end signal. The logical sum of the count end signals of the N counters is taken by the OR gate, and the logical sum signal is delayed by the clock resolution by the last means.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a digital delay circuit according to an embodiment of the present invention. The digital delay circuit shown in FIG. 1 has a frequency divider circuit 1 for dividing an input signal, prescalers 2 and 3 capable of controlling a start point for dividing a clock by an output of the frequency divider circuit 2 and a prescaler 2. , A counter 4, which counts the output of 3,
5, an OR gate 6 that ORs the counting end signals of the counters 4 and 5, a demultiplexer 7 controlled by the delay amount input 20, continuously connected D flip-flops 8 to 11 that function as shift registers, and It consists of OR gates 12-14.

Next, the operation of the digital delay circuit configured as described above
This will be described using the timing chart in the figure. In this embodiment, the prescalers 2 and 3 are divided by 4 and the delay amount in the operation timing chart of FIG. 2 is set to 15 clocks.

When the input signal 21 is input to the frequency-dividing circuit 1, the frequency-dividing circuit 1 outputs frequency-divided signals 22 and 24. 2 divided signal 2
The prescaler 2 receiving 2 outputs the divide-by-4 clock 23 which controls the dividing start point. 2 divided signal 22 and 4 divided clock
23 is input to the counter 4, and the delay amount 20 is taken in at the rising edge of the divide-by-4 clock 23 while the divide-by-2 signal 22 is at the “L” level. Count three, and output a count end signal 26. On the other hand, the prescaler 3 and the counter 5 also operate in the same manner, and the counting end signal
Outputs 27. The OR signals 6 are ORed with the counting end signals 26 and 27 and are input to the enable input E of the demultiplexer 7. The demultiplexer 7 receives the enable input E from the output terminal Z3 which is preselected by the delay amount 20.
The count end signal 28 input to is output. Since each output of the demultiplexer 7 is input through the OR gates 12 to 14 to the D flip-flops that operate by the clock 30, the number of passing stages of the D flip-flops 8 to 11 differs by one, so that four clock cycles are used. The count end signal 28 delayed by an integer multiple resolution is further delayed by a resolution of the cycle of the clock 30 to obtain a delay signal 29.

As described above, according to the present embodiment, by providing the prescaler in the front stage of the counter that delays and the shift register that delays with the clock resolution in the rear stage, the high frequency of the clock can be obtained without being limited by the operating frequency of the counter. The delay resolution can be improved. Further, the counting end signals of the two counters provided for expanding the variable delay range are ORed, and then the D flip-flop takes the cycle of the clock, so that the propagation delay time between the counters is reduced. The jitter of the delay signal due to the variation is removed.

In this embodiment, two sets of the prescaler and the counter are provided. However, in order to expand the setting range, the number of sets of the prescaler and the counter is increased and the frequency division number of the frequency dividing circuit for dividing the input signal is set. Match the numbers. The essence of the present invention is not damaged by changing the number of sets. Furthermore, although the frequency division number of the prescaler for dividing the clock is described as 4, the present invention is not limited to this.
If the prescaler frequency division number is further increased, the number of D flip-flop connections and the number of demultiplexer outputs that delay at the clock cycle may be increased.

〔The invention's effect〕

According to the present invention, it is possible to widen the delay range and obtain a delay output with high resolution without jitter.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a digital delay circuit according to an embodiment of the present invention, and FIG. 2 is an operation timing chart of the digital delay circuit shown in FIG. 1 ... 2 frequency divider circuit, 2,3 ... Prescaler, 4,5 ... Counter, 6,12-14 ... OR gate, 7 ... Demultiplexer,
8-11 …… D flip-flop.

Claims (1)

[Claims] 1. A means for receiving an input signal, generating N divided outputs in which a period N times the period T of the input signal is shifted by T, and dividing a clock by receiving each divided output signal. N counters for counting the divided clocks, an OR gate for ORing the count end signals of these N counters, and the output signal of the OR gate for the clock cycle Digital delay circuit consisting of means for delaying with resolution.