JPH0754899B2 - Level shift circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit used in an integrated circuit using GaAs.

[0002]

2. Description of the Related Art Up to now, a level shift circuit used in an integrated circuit using GaAs has used a circuit as shown in FIG. 5 (RL Van Tuyl, CALiechti, "High-spee".
d integrated logic with GaAs MESFETs "IEEE JOURNAL
OF SOLID-STATE CIRCUITS, VOL.sc-9, NO.5 OCTOBER 197
4 pp.269-276). This is a level shift circuit using a diode. With respect to the output potential of the transistor Q51 which constitutes the source follower in the level shift circuit of the output stage, the level shift diodes D51 to D53 are provided.
The cascade connection of (1) shifts the potential according to the potential drop corresponding to the number of stages of the junction potential (approximately 0.8 V) of the stacked thyroids.

Since the level shift circuit using such a diode causes a potential drop due to the junction potential of the diode, in principle, the output potential can only be controlled for each integral multiple of the junction potential. Met.

[0004]

In the level shift circuit using the diode, the output potential can only be shifted according to the level shift amount determined by the junction potential of the diode.

The present invention provides a level shift circuit capable of arbitrarily controlling the shift amount of the output potential.

[0006]

According to the present invention, a first Schottky gate type field effect transistor forming a source follower by inputting an input potential to a gate, a constant potential is applied to a drain and a bias is applied to a gate. The second
A Schottky gate type field effect transistor having a drain electrode and a gate electrode short-circuited in series between the Schottky gate type field effect transistor and the Schottky gate type field effect transistor. A level shift circuit using an electrode or a source electrode as an output terminal.

[0007]

FIG. 1 is a diagram showing the basic configuration of the level shift circuit of the present invention. The transistor Q1 is a Schottky gate type field effect transistor which constitutes a source follower. The transistor Q2 is a Schottky gate type field effect transistor that functions as a current source when biased. The transistors Q3 and Q4 are Schottky gate type field effect transistors for level shift in which the gate and drain electrodes are short-circuited.

The operating principle of this level shift circuit will be described. Here, it is assumed that the transistors Q1 to Q4 are designed to have the same characteristics. When a bias Vg is applied to the transistor Q2, a current corresponding to the bias value flows. At this time, currents having the same value also flow in the transistor Q1, so that a voltage equal to the voltage between the gate and source of the transistor Q2 is generated between the gate and source of the transistor Q1. As a result, when the potential Vin is applied to the input end, the gate of the transistor Q1
A potential level-shifted by the source-source potential Vg is output. This level shift amount is the gate of the transistor Q2
Since it is determined by the potential between the sources, the level shift amount of the output terminal out1 can be determined by determining the bias applied to the transistor Q2.

Next, the level shift at the output terminals out2 and out3 will be described. The transistors Q3 and Q4 are connected to the gate and drain electrodes, respectively, and have a so-called diode-connected configuration. Where transistor Q
The potential difference between the source and drain of each of 3 and Q4 is given by the potential difference between the source and gate. Since this is determined by the VI characteristics of the transistor, by setting the current value appropriately, for example, the transistors Q3, Q4
It is also possible to set the voltage between the gate and the source to about 0.4V. This makes it possible to construct a level shift circuit having a smaller shift voltage, which could not be realized by the level shift circuit using the diode.

That is, according to the present invention, since the level shift voltage is determined by the gate-source voltage of the cascade-connected transistors, the level shift amount of the output is arbitrarily set according to the characteristics of the transistor and the bias potential applied. It becomes possible to do.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 2, the level shift circuit of the present invention is used in the output stage of the differential input circuit. All FETs are normally-off type. Further, Q13, Q17 and Q21 are current sources of normally-off type FETs having a common gate potential.
Also, the bias circuit uses Q13 and Q through the bias line.
17, it has a role of giving a bias voltage to the gate potential of Q21.

The operation of this circuit will be briefly described. When the input terminal A1 is at "1" level (A2 is at "0" level) RL1
The current determined by is flowing through Q11. When this current flows through RL1, the gate potential of Q14 becomes low, the output terminal B1 shows "0" (the output terminal C1 is "1") level,
Inverter operation.

Here, Q15, Q16, Q19, and Q20 are level shift transistors having their drain and gate electrodes connected, respectively. The output voltage level-shifted by the potential difference generated between the gate and the source of these transistors can be taken out. Since the level shift amount of the output voltage is determined by the VI characteristic of each transistor, the shift amount can be set by the value of the current flowing through the transistor.

Since the current flowing through the transistors Q15 and Q16 is equal to the current flowing through the transistor Q17 and the current flowing through the transistors Q19 and Q20 is equal to the current flowing through the transistor Q21, the current flowing through the transistors Q15 and Q16 or the transistors Q19 and Q20. Setting the currents sets the currents flowing to the transistors Q17 and Q21, respectively. Therefore, if the bias applied to the transistors Q17 and Q21 by the bias circuit is variable and can be set appropriately, the level shift amount of the output can be arbitrarily set by the applied bias.

Next, a configuration example of the bias circuit is shown in FIG. Fig. 3 shows resistors R31 and R32 and normally-off type FET Q3
This is a bias circuit composed of 1 and Q32. This is done by inserting the transistor Q31 between the gate and drain electrodes of the transistor Q32 to increase the gate-drain voltage of Q32. R32 determines the drain current of Q31. Of course, the current is set to a current that does not turn on the Schottky diode by setting the gate-source voltage of Q31 to about 0.4V. Transistor Q in Figure 2
When 13 and the FET of the transistor Q32 in FIG. 3 have the same size, both transistors have the same current value due to the current mirror circuit operation.

FIG. 4 shows another configuration example of the bias circuit shown in FIG. This is because the diodes D1 to Dn are inserted between the source electrode of the transistor Q41 and the gate electrode of the transistor Q42 so that when the outside air temperature changes, the current of the transistor Q42 is compensated by the temperature characteristic of the resistor R41 and the diode. It is devised so that it does not change. In addition, the voltage between the drain and the source of the transistor Q42 is set large.

As described above, the level shift circuit of the present invention can be widely used as a circuit for performing level shift of input and output of so-called "Source Coupled Logic".

In the level shift circuit shown in FIG. 1, transistors (transistors Q3 and Q4) having gate / drain electrodes connected to each other are cascaded in two stages to realize output level shift. The number of is not limited to two, and can be changed as needed.

In the description of the level shift circuit shown in FIG. 1 above, it is assumed that the transistors Q1 to Q4 have equal characteristics, but by designing transistors having different characteristics, the level shift width at the output terminal can be reduced. It is possible to change. When transistors having the same characteristics are used, equal currents flow through the transistors Q1 to Q4. Therefore, for example, the gate widths and threshold voltages of the transistors Q3 and Q4 are designed to be different from the characteristic values of the transistors Q1 and Q2. Then, the shift width at the output end can be set to a smaller voltage. This makes it possible to set a finer shift width for the output voltage.

[0020]

In the level shift circuit according to the present invention, since the shift width of the output voltage can be given by the potential between the gate and the source of the transistor, the shift amount of the output potential can be controlled arbitrarily. Becomes

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a level shift circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of a level shift circuit of the present invention.

FIG. 3 is a diagram showing a configuration example of a bias circuit.

FIG. 4 is a diagram showing a configuration example of a bias circuit.

FIG. 5 is a diagram showing an example of a conventionally used level shift circuit.

[Explanation of symbols]

 Q1 to Q52 Transistors RL1 to RL2, R31 to R42 Load resistance D1 to D53 Diode

Claims (2)

[Claims] 1. A first Schottky gate type field effect transistor having a gate electrode supplied with an input potential, and a drain.
A reference potential is supplied to the gate electrode and a predetermined bias is applied to the gate electrode
Second Schottky gate type field effect supplied with potential
Between the transistor and the drain and gate electrodes
Shorted third Schottky gate field effect transistor
This third Schottky gate type electric field by connecting a transistor
Output the drain or source electrode of the effect transistor.
In the level shift circuit using the output terminal,
Gate potential of the Yottky gate type field effect transistor
By adjusting the predetermined bias potential supplied to
For the third Schottky gate field effect transistor
A level shift circuit characterized in that a level shift voltage is set . 2. A fourth and fifth Schottky gate type field effect transistors having source electrodes connected in common, a common source electrode of the fourth and fifth Schottky gate type field effect transistors, and a reference potential . Between the
The output potential of a differential input circuit including a sixth Schottky gate type field effect transistor whose gate electrode is supplied with a predetermined bias potential is set to the input potential of the first Schottky gate type field effect transistor. The level shift circuit according to claim 1.