JPH0754903B2 - 3-phase PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a three-phase PLL circuit.

B. Outline of the Invention In the three-phase PLL circuit according to the present invention, the output signals of the three phase comparators are converted into phase difference voltage signals via the low-pass filters, and these voltage signals are compared and amplified by two amplifiers. Input to two voltage-controlled oscillators, and the output signals of these oscillators are compared with the input signal by a phase comparator to obtain outputs of 120 ° phase difference and 240 ° phase difference at the same time. It was made possible.

C. Conventional Technology As shown in FIG. 11, the PLL circuit includes a phase comparator 1, a low pass filter 2, an amplifier 3 and a voltage controlled oscillator 4 (hereinafter referred to as VCO).
Called)). The phase comparator 1 receives the input signal fin
And the phase difference between the output signal f out of VCO4 and VCO4. The phase difference output voltage of the phase comparator 1 is smoothed by the low-pass filter 2, amplified by the amplifier 3, and input to VCO4. This input signal acts as the control voltage for VCO4,
The frequency of the output signal f out of the VCO 4 is automatically controlled to the frequency of the input signal f in.

In the PLL circuit configured as described above, as shown in FIG. 12, the input signal voltage f in (FIG. A) and the output voltage signal f of VCO4 f
When out (Fig. b) is given to the phase comparator 1, an error signal waveform as shown in Fig. c is output to the output. This signal is converted by the low-pass filter 2 into the phase difference signal shown in FIG.

D. Problems to be Solved by the Invention As described above, in the conventional PLL circuit, the output signal of the VCO4 outputs an output having a phase difference of 90 ° with respect to the input signal. Therefore, the conventional PLL circuit cannot obtain an output signal having a phase difference other than 90 ° with respect to the input signal.

E. Means for Solving Problems The first invention is to provide three phase comparators and a low-pass filter, compare the outputs of these low-pass filters with two amplifiers, and input them to two VCOs respectively. , One of the phase comparators performs phase comparison of both outputs of the VCO, and the other phase comparator compares the input signal f ₁ with the output signals f ₂ and f _{3 of} each VCO separately. Is.

The second aspect of the invention is to input the output signals f ₂ and f ₃ to a phase phasing device for phasing.

F. The working input signal f ₁ and the output signals f ₂ and f ₃ are compared by the phase comparator, and the outputs of these comparators are f ₂ −f ₁ , f ₃ −f ₂ and f ₃ −f ₁
Get the output signal of. These output signals are input to the low pass filter, and the predetermined phase difference voltage signals ₁₂ , ₂₃ and ₃₁ are obtained at the outputs. Apply _{23 of} these voltage signals to the positive and negative inputs of one of the two amplifiers,
₁₂ and ₃₁ are applied to the other negative and positive inputs of the amplifier for amplification. These amplifiers outputs ₂₃ - ₁₂ and ₃₁
- ₁₂ output signal is input to the VCO, 120 ° at its output
It outputs the output with a phase difference of 240 °.

The second invention is such that the output signal obtained as described above is input to a phasing device to obtain a phasing output.

G. Example First, the principle of the present invention will be described with reference to FIGS. In FIG. 2A, when an input signal f ₁ satisfying the following equations (1) and (2) is given, three-phase alternating current of output signals f ₂ and f ₃ separated by 120 ° can be obtained.

_{f 2 ≒ f 1 + (23} - 12) · K ......... (1) f 3 ≒ f 1 + (31 - 23) · K ......... (2) where, _{12, 23, 31} f _1, f The phase angle between ₂ and f ₃ , K is a constant.

Now, it is assumed that ₁₂ when the output signal f ₂ is shifted like f ₂₁ shown by the broken line in FIG. 2B is 60 °. Then ₂₃ - ₁₂ = 18
0 ° -60 ° = 120 °, and from the formula (1), f ₂ increases to f ₁ + 120K. Then, a force for correcting f ₂₁ in the clockwise direction is generated as shown in FIG. 2c, and the state returns to the steady state shown in FIG. 2d.
At this time, ₁₂ = ₂₃ = ₃₁ = 120 °, and (1),
From the equation (2), f ₂ = f ₁ and f ₃ = f.

An example obtained based on the above principle will be described below.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, PC _{1 to} PC ₃ are _{first to third} parts each composed of a multiplier.
In the phase comparator, the input signal f ₁ is supplied to the first inputs of these first and third phase comparators PC ₁ and PC ₃ , and the output signals f ₂ of VCO ₁ and VCO ₂ are supplied to their second inputs. , f ₃ is supplied. The second
The output signals f ₂ and f ₃ of VCO ₁ and VCO ₂ are supplied to the _first and second inputs of the phase comparator PC ₂ . Output signal of each PC _{1 to} PC ₃ f ₂ −f ₁ , f ₃
−f ₂ and f ₃ −f ₁ are the first to third low pass filters LPF, respectively.
₁ is inputted to ~LPF _3, the output signal (phase difference voltage) at the output of the _{LPF 1 ~LPF 3 12, 23,} 31 obtained. The output signal of the LPF ₁ is supplied to the negative input of the first amplifier OP _1, the output signal of the LPF ₂ is the positive input terminal of the first amplifier OP ₁ and a second amplifier O
It is supplied to the negative input terminal of P ₂ . The output signal of LPF ₃ is supplied to the positive input terminal of the second amplifier OP ₂ . Both amplifier OP _1, OP ₂ output signals ₂₃ - _{12, 31} - ₁₂ and VCO ₁
Input to VCO ₂ respectively.

Next, the operation of the above embodiment will be described.

FIG. 3 is a time chart of the three-phase PLL circuit, which shows the input signal f ₁
On the other hand, the voltage waveforms in each process until the output signals f ₂ and f _{3 of} the first and second VCO ₁ and VCO ₂ are locked are shown. That is, the output signal f ₂ of the _first VCO ₁ is the third with respect to the input signal f ₁ (Fig. 3a).
As shown in FIG. 6B, the phase shifts to 60 °, 70 ° and 80 °, and then comes to a position shifted 120 ° from the input signal f ₁ . Then the first amplifier OP ₁
The output of is locked in this state by zero. On the other hand, the second V
The output signal f ₃ of CO ₂ is shifted from the input signal f ₁ by 300 °, 310 °, ... And is locked at a position delayed by 240 ° from the input signal f ₁ . In the figure, the first phase comparator PC1 and the second phase comparator P
Each output signal of C2 and the third phase comparator PC3 has a voltage comparator of f ₁ × f ₂ , because the phase comparator is composed of a multiplier.
Since f ₂ × f ₃ and f ₁ × f ₃ are obtained, the waveforms shown in FIGS. 3 (d), (e) and (f) are obtained. The output signals of the first, second and third low pass filters, LPF ₁ , LPF ₂ and LPF _{3 12
23} - ₃₁ Fig. 3 g, h, the output becomes a variation shown in i, further first amplifier OP _1, the second amplifier OP ₂ of the output signals ₂₃ - _12,
31 - ₂₃ is the output variation shown in FIG. 3 j, k.

Now, paying attention to the output signal f ₂ of the _first VCO ₁ ,
The output signal of the amplifier OP ₁ has a negative level as shown in FIG. The output signal ₂₃ of the negative level - ₁₂ first
Since it is input to the _first VCO ₁ shown in the figure, the frequency of the output signal f ₂ is lowered and the output signal f _{1 is out} of phase by 120 °. At this point, the output of the first amplifier OP ₁ becomes zero, and it is locked in this state.

Similarly, for the output signal f ₃ of the _second VCO ₂ , the second amplifier OP 2
Since the output signal of is positive level as shown in FIG.
The frequency of the output signal f ₂ of the _second VCO ₂ shown in the figure rises and is locked at a position 240 ° apart from the input signal f ₁ .

When the input signal f ₁ is input to the circuit shown in FIG. 2 as described above, it is possible to generate the output signals f ₂ · f ₃ for the three-phase alternating current. Note that FIG. 4 shows the output signal f of the _first VCO ₁ .
₂ and the first amplifier OP ₁ of the output signal ₂₃ - ₁₂ the relationship between illustrates the phase difference.

Next, a second embodiment of the present invention will be described.

In the three-phase PLL circuit of the first embodiment, there are cases where the output signals f ₂ and f ₃ have a positive phase region and a negative phase region as shown in FIG. 5, which is not preferable. For example, as shown in FIG. 6, the negative phase region is in a state of poor stability and normally becomes a more stable positive phase state. FIG. 7 shows the change in the above state. Here, as shown in FIG. 7, focusing on the output signal f ₂ , for example, when the output signal f _{2 of the first} VCO ₁ fluctuates at the time point b, the phase is opposite to that of the signal f _1. The phase advances and becomes a positive phase at the time point c. In this way, it is in equilibrium even in the reverse phase, but if the VCO fluctuates even a little, it immediately becomes the positive phase.

The second embodiment is an additional phasing circuit of the three-phase PLL circuit that holds the output signal of the three-phase PLL circuit formed in the first embodiment in the positive phase. FIG. 8 is a block diagram showing the basic configuration. In the figure, 29 is a three-phase PLL of the first embodiment, and 30 is a phasing circuit. The phase comparator 31 outputs the output signal f _{2 of the} three-phase PLL
And f ₃ are input, it is determined which one of these signals leads the phase, and when it is determined that the output signal f ₃ leads the output signal f ₂ , the switching signal is sent to the multiplexer 32. To do. The multiplexer 32 switches between the output signals f ₂ and f _{3 according} to the switching signal and outputs the phasing output signal f
_{Sends 32} and f ₃₃ .

FIG. 9 shows an example of a concrete circuit of the three-phase phase adjuster. In the figure, the phase comparator 31 includes three flip-flops FF31a.
To FF31c and AND circuits AND31e and 31f, the output signal f ₂ is the set terminal S of FF31a and the clock terminal CLK of FF31b.
Is supplied to. The output signal f ₃ is clock terminal C of the FF31a
It is supplied to the set terminals S of LK and FF31b. The output signal of FF31a is set to SET terminal of FF31c, and the output signal of FF31b is F
It is given to the clear terminal CLR of F31c, respectively. FF31c above
Output Q signal and FF31b output signal are AND circuit AND31
In a, the output signal of the FF31a and the output signal of the FF31c are input to the AND circuit AND31b. The multiplexer 32 includes a multiplexer MUX32a including an OR circuit 42 that inputs the output signals of the AND circuits 40 and 41, and a multiplexer MUX32b including an OR circuit 45 that inputs the hand force signals of the AND circuits 43 and 44. . The input terminal of the AND circuit 40, 43, the output signal f ₂ via the Deirei circuit 34b is input, also the output signal f ₃ is input through the Deirei circuit 34c to the first input terminal of the AND circuit 41 and 44 It The output signals of the AND circuits 31a and 31b of the phase comparator 31 are applied to the second input terminals of the AND circuits 41 and 43 and the second input terminals of the AND circuits 40 and 44, respectively. Further, the output signal f ₁ becomes the output signal f ₃₁ via the delay circuit 34a, and the respective output signals of the OR circuits 42, 45 become f ₃₂ , f ₃₃ . The above delay circuits 34a, 34b, 34c are
Since it takes time for the multiplexer to operate,
The purpose is to delay the clock and finish the switch to the destination. The delay circuits 34a, 34b, 34c are for removing spike noise generated at the time of switching.

FIG. 10 is a Taimuchiyato the second embodiment, even if this Taimuchiyato is the output signal f ₂ of a three-phase PLL circuit 29 is delayed from the output signal f _3, even when the advanced phase phasing unit
The output signals f ₃₂ and f ₃₃ are not reversed by 30.

H. Effect of the Invention As described above, according to the present invention, the phase difference of 120 ° and 240 ° can be obtained at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the principle of the present invention, FIG. 3 is a time chart of a three-phase PLL, and FIG. 4 is an input signal f ₁ And the first
And the output signal f ₂ of VCO _1, a first amplifier output signal ₂₃ - explanatory diagram showing the phase difference relationship between the _12, for comparison with the positive phase and the negative phase of Fig. 5 3-phase PLL signal Taimuchiyato, the Figure 6 shows three-phase PL
A characteristic diagram showing the relationship between the positive and negative phases of the L circuit, Fig. 7 shows 3
A time chart of each process when the reverse phase of the phase PLL circuit is returned to the normal phase, FIG. 8 is a configuration diagram showing a second embodiment of the present invention, and FIG. 9 shows a specific configuration of FIG. Block diagram, FIG. 10 is a time chart of a three-phase phasing device, FIG. 11 is a block diagram of a conventional PLL circuit configuration, and FIG. 12 is a time chart of each process of a conventional PLL circuit. f ₁ …… Input signal, f ₂ · f ₃ …… Output signal, PC ₁ , PC ₂ , PC ₃ …
... 1st, 2nd, 3rd phase comparators, LPF ₁ , LPF ₂ , LPF ₃ ... 1st, 1st
2, 3rd low-pass filter, OP ₁ , OP ₂ ...... 1st, 2nd amplifier, VCO ₁ , VCO ₂ ...... 1st, 2nd voltage controlled oscillator, 29 ...... 3
Phase PLL circuit, 30 ... Phase adjusting circuit, 31 ... Phase comparator, 32 ...
… Multiplexer, FF31a, FF31b, FF31c …… Flip
Float, AND31a, AND31b ... AND circuit, MUX32a, MUX3
2b ... multiplexer, 34a, 34b, 34c ... delay circuit.

Claims (2)

[Claims] Claims: 1. First, second and third phase comparators and first, second converters provided corresponding to these phase comparators for individually converting the output signals of these comparators into phase difference voltage signals. And a third low-pass filter, a first amplifier of which the output signal of the first low-pass filter is input to the negative input terminal and the output signal of the second low-pass filter is input to the positive input terminal of the low-pass filter, and the low-pass filter The output signal of the second low-pass filter to the negative input terminal,
A second amplifier to which an output signal of the third low-pass filter is input to a plus input terminal; and a first voltage-controlled oscillator to which an output signal of the first amplifier is input and which outputs an oscillation output signal controlled by the signal. A second voltage controlled oscillator for receiving an output signal of the second amplifier and transmitting an oscillation output signal controlled by the signal; and inputting an input signal (f ₁ ) to the _first and third phase comparators 1 and the oscillation output signals (f ₂ ) and (f ₃ ) of the second voltage controlled oscillator are given separately, and the oscillation output signals (f ₂ ) of the first and second voltage controlled oscillator are given to the second phase comparator. , (F ₃ ) is applied to the three-phase PLL circuit 2. First, second and third phase comparators, and first, second converters provided corresponding to these phase comparators for individually converting the output signals of these comparators into phase difference voltage signals. And a third low-pass filter, a first amplifier of which the output signal of the first low-pass filter is input to the negative input terminal and the output signal of the second low-pass filter is input to the positive input terminal of the low-pass filter, and the low-pass filter The output signal of the second low-pass filter to the negative input terminal,
A second amplifier to which an output signal of the third low-pass filter is input to a plus input terminal; and a first voltage-controlled oscillator to which an output signal of the first amplifier is input and which outputs an oscillation output signal controlled by the signal. A second voltage controlled oscillator for receiving an output signal of the second amplifier and transmitting an oscillation output signal controlled by the signal; and inputting an input signal (f ₁ ) to the _first and third phase comparators 1 and the oscillation output signals (f ₂ ) and (f ₃ ) of the second voltage controlled oscillator are given separately, and the oscillation output signals (f ₂ ) of the first and second voltage controlled oscillator are fed to the second phase comparator. , (f ₃₎ gave a fourth phase comparator for comparing the phase of the oscillation output signal (f ₂₎ and (f _3), the oscillation output signal (f ₂₎ and is (f ₃₎ given multiplexer And the multiplexer is switched and controlled by the output of the fourth phase comparator. 3-phase PLL circuit oscillation output signal (f ₂₎ and (f ₃₎ is characterized in that so as not to reverse phase.