JPH0756506B2 - Pattern generator - Google Patents

Description

The present invention relates to an improvement of a pattern generator used in, for example, an analog LSI tester.

[Prior Art] There is a type of pattern generator configured to selectively take out a predetermined pattern from a pattern memory by performing an address operation under microprogram control, and a digital device such as a memory device or a VLSI device. Widely used to measure

By the way, digital servo controller, digital TV,
In the measurement of analog LSIs used in electronic exchanges, etc., it is common to check signals successively between the pattern generator and the LSI under test (hereinafter referred to as DUT).

FIG. 3 is a block diagram showing an example of such a conventional pattern generator. In FIG. 3, 1 is a micro memory, 2 is a sequencer, 3 is a pattern memory, and 4 is an LSI to be an inspection object (hereinafter referred to as DUT). An address ad is added to the micro memory 1 from the sequencer 2 via the micro address bus, and the micro memory 1 outputs data dt, instruction is, etc. to the sequencer 2 according to the address ad. A clock ck is externally applied to the sequencer 2 and a pattern response signal Spr is applied from the DUT 4. And sequencer 2
Outputs the address ad to the pattern memory 3. The pattern memory 3 outputs a predetermined pattern pt according to the address ad added from the sequencer 2 to the DUT 4. The DUT 4 outputs the response signal Spr to the sequencer 2 as described above by receiving the pattern pd added from the pattern memory 3.

However, in such a conventional device, since the movement of the microprogram is controlled by the output rate of the pattern and the unique timing, it is not possible to confirm the signal with the DUT 4 at a resolution higher than the operation clock. .

That is, in the measurement of DUT4, it is desirable that the pattern pd added to the DUT4 from the pattern generator is successively and continuously changed without dead time as shown in FIG. As shown in FIG. 4 (b), it is necessary to provide an instruction cycle having an indefinite dead time Td for performing the determination operation in the pattern generator for each pattern pd.

[Problems to be Solved by the Invention] As a result, the pattern pd added to the DUT 4 from the pattern generator becomes indeterminate unless the fixed time Tu following the dead time Td is considered as the pattern to be given to the DUT 4, Since the time Tm required from the change of the pattern pd to the measurement using the pattern pd becomes long, the series of measurement time becomes long. This also makes tuning the program difficult.

The present invention has been made paying attention to these points, and an object of the present invention is to enable the pattern to be changed asynchronously with the clock of the microprogram so as to maintain the continuity of the pattern and prevent the occurrence of a cycle which becomes a dead time. It is an object of the present invention to provide a pattern generator capable of preventing measurement to shorten the measurement time and performing measurement at any time.

[Means for Solving Problems] The present invention which achieves such an object is to provide at least two systems of pattern generation circuits for performing an address operation according to microprogram control and outputting a predetermined pattern from a pattern memory, and an inspection object. The multiplexer that adds the pattern output from the predetermined pattern generation circuit to the inspection object switched by the controller to which the response signal from is input, and the pattern generation instructed according to the system switching command included in the response signal from the inspection object And a pattern designation pointer circuit for adding a signal designating a pattern to be output to the circuit.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 3 are designated by the same reference numerals. In Figure 1, Figure 3 is a micro memory 1 ₁ configured similarly, the sequencer 2 ₁ and pattern memory 3 ₁ made of a first pulse generator circuit (hereinafter # 1 hereinafter) and micro memory 1 _2, the sequencer 2 ₂ And a pattern generating circuit of two systems including a second pulse generating circuit (hereinafter referred to as # 2) composed of the pattern memory 3 ₂ , and these pattern memories 3 ₁ , 3
The outputs pda and pdb of ₂ are applied to the DUT 4 via the multiplexer 5. Reference numeral 6 is a pattern designation pointer circuit, and its output signal Spt is applied to the pattern memories 3 ₁ and 3 ₂ via the demultiplexer 7. The pattern designation pointer circuit 6 stores in advance the address of the pattern to be changed according to the response signal Spr added from the DUT 4. Reference numeral 8 denotes a controller, which outputs a control signal to each unit according to the response signal Spr added from the DUT 4. That is, the controller 8 outputs the load signal Sl to the pattern designation pointer circuit 6, the switching signals Sm ₁ and Sm ₂ to the multiplexer 5 and the demultiplexer 7, and the sequencer 2
_1, 2 ₂ signal Spra associated with the response signal Spr of DUT 4, outputs Sprb, start / stop signal Sss to the clock generator 9
Is output. The clock generator 9 outputs the pattern rate clocks ck ₁ and ck ₂ to the sequencers 2 ₁ and 2 ₂ .

The operation of the apparatus thus configured will be described.

Each micro memory 1 _1, 1 ₂ the same or different programs are loaded, respectively, the first is activated simultaneously. Then, the response signal Spr from the program and DUT4 loaded in each of these micro memories 1 ₁ and 1 ₂
Predetermined pattern pd pattern memory 3 in accordance with the output of the pattern designating pointer circuit 6 driven in accordance with ₁ and 3 ₂
Will be output to DUT4 continuously or alternately.

Figure 2 is a such an operation explanatory diagram, (a) represents the address ad ₁ output from the sequencer 2 ₁ in the pattern memory 3 ₁
(B) shows the clock ck ₁ applied to the sequencer 2 ₁ from the clock generator 9, and (c) shows the sequencer 2 ₂
The address ad ₂ to be output to the pattern memory 3 from _2, (d) shows the clock ck ₂ applied from the clock generator 9 to the sequencer 2 _2, (e) the response signal Spr applied to the controller 8 from DUT4 (F) shows the output of the pattern designation pointer circuit 6, and (g) shows the pattern pd added to the DUT 4 via the multiplexer 5. As is apparent from FIG. 2, the pattern pda is initially output from the # 1 system, and the response signal Spr is output from the # 2 system.
Is added and the output Spt of the pattern designation pointer circuit 6 is added to start generation of the pattern pdb.

First, the address ad from the sequencer 2 ₁ to the pattern memory 3 _{1
It is} assumed that, for example, "100" is added as ₁ , and the pattern pda corresponding to this address "100" is added as a pattern output pd from the pattern memory 3 ₁ to the DUT 4 via the multiplexer 5. Clock ck at time t ₁ in this state from the clock generator 9 to the sequencer 2 _{1
When 1} is added, sequencer 2 ₁ to pattern memory 3 ₁
The address ad ₁ added to the address is changed to, for example, “101” according to the program, and the pattern pda corresponding to the address “101” is output from the pattern memory 3 ₁ to the DUT 4 via the multiplexer 5. # 1 like this
Response signal including an instruction to switch from the # 1 system to the # 2 system from the DUT 4 to the controller 8 at time t ₂ when the pattern pda corresponding to the address "101" is output from the system
When Spr is added, the controller 8 a switching signal Sm ₁ for outputting a pattern memory 3 _second pattern pdb to the multiplexer 5 is added, the load signal Sl addition to the pattern specified pointer circuit 6, the pattern designating pointer to the demultiplexer 7 A switching signal Sm ₂ for adding the output Spt of the circuit 6 to the pattern memory 3 ₂ is added, and signals Spra and Sprb for switching the address system in relation to the response signal Spr of the DUT 4 are output to the sequencers 2 ₁ and 2 _2. , Clock c to the clock generator 9
Add signal Sss to start the output of k ₂ . Thus, the clock ck ₂ from the clock generator 9 to the sequencer 2 ₂
It is added, so that the output Spt pattern designating pointer circuit 6 is loaded into the pattern memory 3 _2. In this embodiment, the pattern designating pointer circuit 6 from the "201" via the multiplexer 5 from the pattern memory 3 ₂ loaded DUT4 pattern pdb corresponding to the address "201" is output as the address of the pattern memory 3 ₂ Will be done. Then, the pattern p corresponding to the address "201"
When the clock ck ₂ is applied from the clock generator 9 to the sequencer 2 ₂ at time t ₃ when db is output, the address ad ₂ applied from the sequencer 2 ₂ in the pattern memory 3 ₂
Will be pattern pdb corresponding to the address "202" via the multiplexer 5 from altered by the pattern memory 3 ₂ DUT4, for example, to "202" in accordance with a program is output. The start address of each sequencer is determined by the pattern designation pointer. like this#
The state in which the pattern pdb is output from 2 is held until the DUT 4 applies a response signal Spr including a command to switch from the # 2 system to the # 1 system to the controller 8.

With this configuration, there is no dead time involved in changing the pattern, and it is possible to change the pattern at an arbitrary point asynchronous with the clock cycle of the microprogram, and to synchronize the measurement. The measurement time can be shortened because the time required for measurement is unnecessary.

In the above embodiment, an example in which the pattern is changed in synchronization with the DUT response signal has been described, but the pattern is alternately switched from each system each time a clock is applied from each system regardless of the DUT response signal. You may make it output.

[Effects of the Invention] As described above, according to the present invention, the pattern can be changed asynchronously with the clock of the microprogram to maintain the continuity of the pattern, prevent the occurrence of dead time, and reduce the measurement time. It is possible to realize a pattern generator that can be shortened and can perform measurement at any time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing an example of a conventional device, and FIG. 4 is an operation explanatory diagram of FIG. 1 ... Micro memory, 2 ... Sequencer, 3 ... Pattern memory, 4 ... Inspection object (DUT), 5 ... Multiplexer, 6 ... Pattern designation pointer circuit, 7 ... Demultiplexer, 8 ... Controller , 9 ... Clock generator.

Claims (1)

[Claims] 1. A predetermined pattern is generated by switching between at least two systems of pattern generation circuits for performing an address operation according to microprogram control and outputting a predetermined pattern from a pattern memory, and a controller to which a response signal from an inspection object is input. A multiplexer that adds the pattern output from the circuit to the inspection target, and a pattern designation pointer that adds a signal that specifies the pattern to be output to the pattern generation circuit instructed according to the system switching command included in the response signal from the inspection target. A pattern generator comprising a circuit.