JPH0756933B2 - Phase adjustment circuit - Google Patents

Description

The present invention relates to a phase adjustment circuit, and more particularly to a phase adjustment circuit that adjusts the phase of a binarized television signal.

[Prior Art] Conventionally, in this type of phase adjustment circuit, a phase adjustment of a television signal is performed by using a capacitor and a variable resistor, and adjusting the vector sum of the voltages applied to them by the variable resistor. I was going.

[Problems to be Solved by the Invention]

Since the conventional phase adjustment circuit described above is configured to change the voltage applied to the capacitor and the variable resistor for performing the phase adjustment by the variable resistor, the amplitude of the output signal when the phase adjustment is performed is There is a problem that the phase changes greatly and the phase adjustment of the television signal cannot be performed linearly.

The present invention has been made in view of such circumstances,
An object of the present invention is to provide a phase adjustment circuit that does not change the amplitude of a television signal when the phase is adjusted and that can linearly adjust the phase of the television signal.

[Means for Solving the Problems]

In order to achieve the above object, the present invention divides a binarized television signal sent at a clock rate into two systems by a signal obtained by dividing a clock pulse by 1/2, and delays the delayed clock pulse. A phase adjustment circuit for returning to the original binarized television signal of the clock rate at the timing of, and D / A converting this television signal for output, and a delay line for delaying the clock pulse and this delay line And a delay time adjusting means for adjusting the delay time.

According to the present invention, a clock pulse is delayed through a delay line capable of controlling a delay time by an arbitrary time within one cycle of the clock pulse, and the delayed clock pulse is binarized. D / A signal
It is used as the timing signal of the D / A converter for conversion. As a result, the phase difference between the television signal and the reference synchronization signal is achieved by controlling the delay time of the delay line. Therefore, by adjusting the phase of the television signal, the output amplitude of the television signal does not change,
Moreover, the phase adjustment can be performed linearly.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the phase adjusting circuit according to the present invention. In the figure, the phase adjustment circuit includes D flip-flops 10, 12, and 14, a selector 16 with a latch, and D /
The A converter 18, delay lines 20 and 26, a differentiating circuit 24, and switches 22 and 28 for adjusting the delay times of the delay lines 20 and 26, respectively.

In the above configuration, the binarized video signal (television signal) is input from the input terminal 100 to the D terminals of the D flip-flops (hereinafter referred to as DF / F) 10 and 12, respectively.

On the other hand, a clock pulse is input from the input terminal 101 to the D terminal of the DF / F14, and is divided by 1/2 by the DF / F14.
Output to 12 enable terminals EN.

As a result, from DF / F10 and 12, 2 every other clock pulse.
The binarized video signal is output, and the DF / Fs 10 and 12 latch the video signals that are offset by one clock pulse from each other. That is, the video signal input from the input terminal 100 is DF / F10, 1
It is divided into 2 systems by 2.

Further, the clock pulse divided by 1/2 by the DF / F 14 is sent to the delay line 20. The delay line 20 is for coarse adjustment of the delay time, and the delay time can be changed in 10 nsec steps with respect to the clock pulse of 70 nsec cycle by the switch 22. The clock pulse delayed by the delay line 20 is input to the differentiating circuit 24, and the differentiating circuit 24 converts the clock pulse, which has been divided by 1/2, into the clock pulse having the original frequency.

The clock pulse of the original frequency output from the differentiating circuit 24 is input to the delay line 26, and the delay line 26
Is further delayed by. The delay line 26 is provided for fine adjustment of the delay time, and is set to 0 by the switch 28.
The delay time can be changed in 5nsec steps.

The output signals of the DF / Fs 10 and 12 are input to the A and B terminals of the seractor 16 with a latch, respectively. In the selector 16 with a latch, the signal delayed by the delay line 20 is used as a control signal and delayed by the delay line 26. With clock signal
The output signals of DF / F10 and 12 are latched. That is, DF / F
The video signal demultiplexed in 10 and 12 is again converted into a multiplexed signal by the selector 16 with the latch. The selector 16 with a latch has a function of preventing a latch miss caused by shifting the clock.

The output signal of the selector 16 with a latch is input to the D / A converter 18, and the D / A converter 18 D / A converts the clock pulse delayed by the delay line 26 as a timing signal.

In the above circuit, the phase difference of the video output signal (television signal) with respect to the reference synchronization signal can be changed by changing the setting values of the switches 22 and 28 that control the delay times of the delay lines 20 and 26, respectively. You can

〔The invention's effect〕

As described above, in the present invention, the delay of the clock pulse is performed by using the delay line capable of controlling the delay time, and the delayed clock pulse is used as the timing signal of the D / A converter. Therefore, according to the present invention, when the phase adjustment is performed, the amplitude of the television signal does not change, and the phase of the television signal can be linearly adjusted.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to the present invention. 10, 12, 14 ... D flip-flop, 16 ... selector with latch, 18 ... D / A converter, 20, 26 ... delay line, 22, 28 ... switch.

Claims (1)

[Claims] 1. A binarized television signal transmitted at a clock rate is divided into two systems by a signal obtained by dividing a clock pulse by 1/2, and the original clock is again reproduced at the timing of the delayed clock pulse. It is a phase adjustment circuit that returns to a rate binarized television signal, D / A converts this television signal and outputs it. A delay line that delays a clock pulse and a delay that adjusts the delay time of this delay line A phase adjusting circuit comprising: a time adjusting unit.