JPH0758480B2 - Peripheral control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technique in which a plurality of peripheral control devices share a controlled device with each other, and particularly to a load balancing technique.

[Conventional technology]

In an information processing system, a system is often configured by using a plurality of peripheral control devices in order to improve the performance and reliability of the peripheral device subsystem.

Conventionally, for this type of peripheral control device, a method of performing load distribution processing only by software and a data transfer path between a plurality of peripheral control devices sharing a controlled device to distribute the load only between the peripheral control devices There was a way to do.

[Problems to be Solved by the Invention] In the conventional method of performing load distribution only by software, when a plurality of host devices that do not have communication means with each other are connected to each peripheral control device, the software of each host device is connected to each peripheral device. It was not possible to accurately know the load status of the control device. Further, in the peripheral control device having the data buffer, when data transfer or the like is performed with the controlled device asynchronously with the data transfer with the host device, the software cannot accurately know the load condition.

Further, the conventional method of providing the data transfer path between the peripheral control devices has a drawback that the amount of hardware of the peripheral control devices increases. Further, in the method of determining load distribution by the peripheral control device, when each peripheral control device is not connected to the same higher-level device, the peripheral control device causes the other peripheral control device to retry for load distribution. There was a request to the host device. To prevent this, the software needs to prohibit the retry request from the peripheral control device.

[Means for Solving the Problems]

The peripheral control device of the present invention includes a confirmation means for confirming the control information of another peripheral control device, an identification means for storing the identification information of the host device connected for each route connected to the host device, and the recognition result thereof. And a judgment means for judging the optimum peripheral control device based on the identification result, and if the result of the judgment is that the process other than the peripheral control device that made the judgment is valid, the peripheral device is retried to the host device. And means for requesting to do so.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a magnetic tape subsystem which is an embodiment of the present invention.

A magnetic tape controller (hereinafter referred to as MTC) 1 is connected to a host machine 2 and a plurality of streamer type magnetic tape devices (hereinafter referred to as MTU) 3 via a host connection unit (hereinafter referred to as CHA) 10 and a device connection unit (hereinafter referred to as MTA) 11 respectively. It is connected. Each MTU3 is connected so as to be shared by the two MTC1s.

The data buffer 12 of MTC1 is divided corresponding to each MTU3,
It temporarily stores the data transferred between CHA10 and MTA11 and enables asynchronous operation of CHA10 and MTA11. The microprocessor 13 controls each part of the MTC 1. Control information storage
Reference numeral 14 stores various information including control information of the microprocessor 13. The load information storage unit 15 is CHA10 or MTA11.
The status of data transfer (the number of data transfers and the number of data transfers waiting) and the usage status of the data buffer 12 are stored. The data in the load information storage unit 15 can be read out even by the microprocessor 13 of the MTC 1 of the other system to which it is coupled. After the processing requested by the host machine 2 is completed, the status storage unit 16 temporarily stores the status edited by the microprocessor 13 as its execution result and sends it to the host machine 2 via the CHA 10.

The load distribution availability storage unit 17 stores the availability of load distribution processing for each MTU 3 according to an instruction from the host machine 2.
The host identification information storage unit 18 stores identification information unique to each host machine sent from the host machine 2 for each path. The data of the host identification information storage unit 18 can be read also by the microprocessor 13 of the MTC 1 of another system which is coupled to each other.

FIG. 2 shows the information stored in the load information storage unit 15 in FIG. During processing, the instruction count 101 indicates the number of instructions being executed from the host machine 2 to the MTU 3 in each MTC. The buffer use information 102 is assigned with a bit corresponding to each MTU 3, and indicates whether or not the buffer is used in the processing of each MTU 3.

Next, the operation of the apparatus of this embodiment will be described with reference to the drawings.

The microprocessor 13 shown in FIG. 1 controls each unit in the MTC 1 by a micro program, and especially the host machine 2
In response to a READ command, a WRITE command, etc., the CHA 10, MTA 11, and data buffer 12 are controlled to read data from the MTU 3 and write data to the MTU 3.

When the microprocessor 13 receives an instruction from the host machine 2 via the CHA 10, it decodes the instruction and determines whether it can be immediately executed in the MTC 1 without accessing the MTU 3. MT
If it can be executed immediately in C1, execute this instruction, store the status indicating the result in the status storage unit 16, and then
Report via 0 or request next instruction.

The command sent from the host machine 2 to the ATC MTC1 is the first MT
In the case of an instruction to access U3, the microprocessor 13 reads respective load information from the load information storage unit 15 of its own system (A system) and the load information storage unit 15 of another system (B system) and compares them. As a result of the comparison, when it is determined that it is appropriate to process the instruction in the own system, the number 101 of the instructions being processed in the load information storage unit 15 in the own system shown in FIG. 2 is incremented by one. Next, when the buffer is used in the processing of the instruction, the MTU in the data buffer use information 102 of the own load information storage unit 15 is also used.
Set the data buffer in-use bit that is assigned 1 bit for each 3 bits.

When the instruction received from the host machine 2 is a WRITE instruction, the microprocessor instructs the CHA 10 and the data buffer 12 to start data transfer. The data sent from the host machine 2 is sequentially stored in the data buffer 12. When the sent data amount is less than the standard, the operation for MTU3 is not started and the end report or the next command request is issued to the host machine 2. At this time, the number of in-process instructions 101 shown in FIG. Next, when a WRITE command is issued again from the host machine 2 to the same MTU3, the buffer busy bit 102 of the load information storage unit 15 is set, so it is decided to process the command by its own system and data transfer is performed. Is started and stored in the data buffer 12. When the total amount of data in the data buffer 12 with the previously stored data block exceeds the standard value, the microprocessor instructs the MTA 11 to send a WRITE instruction to the MTU 3 and transfer the data. When the data transfer is completed by waiting for the host machine 2 and the data buffer 12, the microprocessor 13
Performs termination processing in the same manner as the previous WRITE command. At this time, the WRITE process is being executed between the data buffer 12 and the MTU3.

Next, the command issued from the host machine 2 is a WRITE command for the second MTU 3, and at this time the data buffer 12 and the first
If the above-mentioned WRITE processing is being performed between the MTUs 3 of the above, the microprocessor 13 reads the respective load information from the load information storage units 15 of the own system and the other system and compares them. As a result, it does not use its own buffer for the MTU3,
If the number of in-process instructions 101 of the other system and the number of drives in the buffer indicated by the buffer usage information 102 are smaller than that of the own system, the MTs of the other system are adjusted to balance the loads of the two MTC1s.
It is appropriate to execute the instruction through C1. Next, the data is read from the host identification information storage unit 18 of each of the own system and the other system, the identification information of the path that received the command is compared with the identification information of each path of the MTC1 of the other system, and there is the same value. To confirm. Further, in the MTC1 of the other system, after confirming that the path having the same identification information is operable, the microprocessor 13 of the own system MTC1 sets the status requesting the retry from the other system in the status storage unit 16. .

The host identification information is sent in advance from each host machine 2 to the MTCs 1 of both systems by an identification information sending command through all the connected paths. The identification information is a unique value for each host machine 2. Also different path, different
Even in the case of MTC, the same information is sent if it is connected to the same host machine 2. The MTC 1 stores the host identification information sent from each host machine 2 in the host information identification storage unit 18 in association with each path. If the data buffer 12 is being used for the MTU3 in another system in addition to the purpose of balancing the load, after confirming that both MTC1s are connected to the same host machine 2, the same status is displayed. It is set in the status storage unit 16 of the own system.

The status is sent to the host machine 2 via the CHA 10 of the A system, and the host machine 2 receiving the status issues a load balancing prohibition command to the MTC 1 of the B system and then reissues a command to be retried. The B-system MTC 1 that has received the load distribution prohibition command sets the portion of the load distribution availability storage unit 17 corresponding to the MTU 3 to the load distribution prohibition mode. After that, the B-system MTC 1 executes the command received from the host machine 2 to the MTU 3 regardless of the load status of both systems. This keeps the load of MTC1 on both systems balanced and prevents unnecessary degradation of performance by requesting more retries from other systems for load balancing.

In the A-system MTC1, when the WRITE process involving data transfer between the data buffer 12 and the first MTU3 is completed and there is no data for the MTU3 in the data buffer 12, the microprocessor 13 causes the load information storage unit 15 Clear the bit corresponding to the MTU3 of the buffer usage information of. In this embodiment, in order to optimize the load distribution according to the change of the load distribution status, when the READ / WRITE processing of a unit of a certain unit such as a file unit or a volume unit ends, the load balancing prohibit mode is released from the host machine. An order is issued. For example, when the host machine issues a load balancing prohibition mode release command to the MTU3 via the A-system MTC1, the A-system microprocessor 13 executes this command, and at the same time executes this command. This command is also transmitted. In accordance with the transmitted instruction, the B system microprocessor also releases the load balancing prohibition mode. The same applies when a load balancing prohibition mode release command is supplied from the host machine via the B system MTC1.

Although the WRITE command has been described above, the same applies to other commands.

In addition, as shown in FIG. 1, when two host machines 2 are connected to each MTC1, load can be distributed by instructions from each MSC1 even if there is no communication means between the host machines. Can be easily analogized.

〔The invention's effect〕

As described above, the present invention provides, between peripheral control devices that share a controlled device, means for comparing mutual load conditions and means for identifying and comparing upper devices connected to each other peripheral control device. , If it is judged that it is more efficient to perform the processing in the peripheral control device of the other system and that they are connected to the same higher-level device, request the higher-level device to retry from the peripheral system control device of the other system. By providing the means, there is an effect that an accurate load balancing process can be realized with a small amount of hardware even when connected to a plurality of host devices or when a large amount of processing is performed asynchronously with the host device. .

[Brief description of drawings]

FIG. 1 is a block diagram of a magnetic tape controller according to an embodiment of the present invention, and FIG. 2 is a diagram showing types and forms of information stored in the load information storage unit 15 shown in FIG. 1 ... Magnetic tape controller, 2 ... Host machine, 3 ...
... magnetic tape device, 10 ... host connection part, 11 ... device connection part, 12 ... data buffer, 13 ... microprocessor, 14 ... control information storage part, 15 ... load information storage part, 16 ... Status storage unit, 17 ... Load distribution availability storage unit, 18 ... Host identification information storage unit, 101 ... Number of processing instructions, 102 ... Buffer usage information.

Claims (1)

[Claims] 1. In a peripheral control device that shares a controlled device with another peripheral control device and is connected to a plurality of host devices, identification information of the host device that is connected for each route connected to the host device. And means for storing the operating status, means for notifying the other peripheral control devices of the operating status and the identification information of the host device, and the stored operating status and the identification of the host device. Means for comparing information with the operating status notified from the other peripheral control device and the identification information of the higher-level device to determine which peripheral control device should perform new processing instructed by the higher-level device. When the determination means determines that a new process should be processed by the other peripheral control device, the higher-level device is requested to retry via the other peripheral control device. Peripheral control apparatus characterized by comprising means that.