JPH0758506B2 - Image processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus suitable for obtaining an original image without reflection noise of an object.

(Prior Art) Conventionally, in this type of image processing apparatus, the shape of an object in a state of being appropriately illuminated is photographed by a television camera, and this photographed image is processed as a binarized image. There is something.

(Problems to be solved by the invention) By the way, in such a configuration, a hole area is formed in the above-described binarized image due to reflection noise of an object with respect to illumination light, etc. The transformed image may be an image different from the one corresponding to the actual shape of the object.

On the other hand, when filling the hole area described above, there is a method of filling the hole area after examining the outer peripheral portion of the hole area in the binarized image, but according to this method, prior to filling, the hole There has been a problem that the image processing becomes complicated because the area must be recognized in advance.

Further, if hardware is used to perform the filling processing at high speed, dedicated hardware is required, which causes a problem of high cost. On the other hand, when trying to perform the filling processing by software, there is a problem in that the processing takes too much time and is not practical.

Therefore, the present invention is intended to perform the above-described fill processing in an image processing apparatus by effectively utilizing both hardware and software in order to deal with such a problem.

(Means for Solving Problems) In solving the problems, the structural features of the present invention are as follows.
A photographing means for photographing a contour image of an object to be photographed, which is irradiated with light from an appropriate light source, as a plane image, and a plane image photographed by the photographing means is binarized and formed as a binarized image. Binarizing means for generating as binarized image data, reference image data generating means for generating as reference image data a reference image having an outer contour capable of surrounding the outer contour of a plane image photographed by the photographing means. Reducing means for reducing the black portion by one pixel along the entire circumference of the reference image generated by the reference image data generating means to generate reduced image data, and reduced image data reduced and generated by the reducing means. First matching means for generating first matching image data by logical product with the binary image data generated by the binarizing means, and the first matching means A matching means including a second matching means for generating second matching image data by an exclusive OR of the generated first matching image data and the reference image data generated by the reference image data generating means; Output means for outputting one matching image data, arithmetic processing using the first matching image data generated by the first matching means as new reference image data, and reducing the new reference image by the reducing means. And a new first matching image by a logical product by the first matching means of the reduced image data and the binarized image data generated by the binarizing means. Calculation processing for generating data, the new first matching image data, and the new reference image data Performs an arithmetic processing to generate a new second matching image data by an exclusive OR by the second matching means,
The above-described respective calculation processes are repeated until the new second matching image data is completely black, and the new second matching image data
It is because the output means is provided with an arithmetic processing means for outputting the new first matching image data when all the matching image data are black.

(Operation / Effect) With the above-described configuration of the present invention, if the photographing means photographs the outline image of the object to be photographed as a planar image, the reference image generating means causes the outer contour of the planar image photographed by the photographing means. Is generated as reference image data having an outer contour capable of enclosing, and the binarizing means binarizes the plane image as binarized image data based on a command sequence of the arithmetic processing means. Then, the reducing means reduces the black portion by one pixel along the entire circumference of the reference image generated by the reference image data generating means to generate reduced image data, and the first matching means reduces the reducing image data by the reducing means. First matching image data is generated by a logical product of the generated reduced image data and the binarized image data generated by the binarizing means, and the second matching means performs the first matching. Second matching image data is generated by an exclusive OR of the first matching image data generated by the encoding means and the reference image data generated by the reference image data generating means.

Then, the arithmetic processing means sets the first matching image data generated by the first matching means as new reference image data, and reduces the new reference image by the reduction means to generate new reduced image data. Then, new first matching image data is generated by a logical product of the reduced image data and the binarized image data generated by the binarization unit by the first matching unit,
The new second matching image data is generated by exclusive OR of the new first matching image data and the new reference image data by the second matching means, and the new second matching image data is all black. The above-described processing is repeatedly performed until, and when the new second matching image data is completely black, the new first matching image data is output to the output unit.

Therefore, if the binarizing means, the matching means including the first matching means and the second matching means, and the reducing means are configured by general-purpose hardware, while the arithmetic processing means is configured by software, these hardware can be used. Due to the synergistic action of the advantages of the software, it is possible to provide an image processing device that can process the above action at high speed with a simple configuration at low cost without recognizing the filled area.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.
The figure shows an example of an image processing apparatus according to the present invention.
The image processing apparatus includes an industrial television camera 10. The television camera 10 captures an object illuminated by appropriate illumination light as a planar image and generates an imaging signal. The A / D converter 20 digitally converts the photographing signal from the television camera 10 to generate a digital signal. The microcomputer 30 follows the flowchart shown in FIG. 2 and includes an A / D converter 20, a binarization circuit 40, an image memory 50, a reduction circuit 60 and a matching circuit 70.
The computer program is executed in cooperation with the computer, and during this execution, the binarization circuit 40, the image memory 50, the reduction circuit 60, the matching circuit 70, and the cathode ray tube 90 (hereinafter, CRT9
The arithmetic processing necessary for controlling the CRT controller 80 connected to (referred to as 0) is performed. The computer program described above is stored in advance in the ROM of the microcomputer 30.

The image memory 50 is composed of a ROM and a RAM. In the ROM of the image memory 50, data representing a rectangular solid fill image G as shown in FIG. 4 (hereinafter referred to as solid fill image data) is stored in advance. Remembered However, this fill image data is specified by the black area corresponding to "0", and the contour of the fill image G matches the outer contour of the background area surrounding the planar image of the object to be photographed. In addition, the RAM of the image memory 50 stores the digital signal from the AD converter 20, and the outputs of the binarization circuit 40, the reduction circuit 60, and the matching circuit 70.

The binarization circuit 40, under the control of the microcomputer 30, reads out the digital signal (that is, the data representing the planar image) from the RAM of the image memory 50 as described later and stores it in association with the predetermined threshold data. The value is converted and stored in the RAM of the image memory 50.

The reduction circuit 60 includes a data controller 61, a RAM 62, and a comparison circuit 63 connected to the data controller 61 and the RAM 62. The data controller 61 controls the image memory 50 under the control of the microcomputer 30.
The transfer of data between the ROM and the comparison circuit 63 is controlled. R
In the AM62, the fill image data, or the first matching formed by the matching circuit 70 as described later.
Predetermined reduction logic data necessary for successively reducing the contour of the black portion corresponding to "0" of the matching image data by one pixel over the entire circumference is stored. Comparison circuit 63
Is the image memory 50 and RA via the data controller 71.
According to each data from M62, the data from the image memory 50 is reduced as described later.

The matching circuit 70 includes a data controller 71, an AND gate 72 and an exclusive OR gate 73 connected to the data controller 71. The data controller 71 exchanges data between the microcomputer 30 and the AND gate 72 and the exclusive OR gate 73 under the control of the microcomputer 30. The AND gate 72 performs a logical product operation of the binarized data and the reduced image data, which will be described later, from the RAM of the image memory 50 via the data controller 71, and inputs it to the RAM of the image memory 50 as the first matching image data. . The exclusive OR gate 73 performs an exclusive OR operation of both data (the fill image data and the first matching image data) from the image memory 50 via the data controller 71 as described later, and outputs an image as the second matching image data. Input to RAM of memory 50.

The CRT controller 80 is the microcomputer 30
The calculation contents of CRT9
The contents of the video signal are displayed on the display surface of 0.

When the apparatus of the present invention is operated in the present embodiment configured as described above, the microcomputer 30 starts execution of the computer program in step 100a according to the flowchart of FIG. 2, and is initialized in the next step 110. I do. Further, when the object to be photographed, which is irradiated with light from above by an appropriate light source, is photographed from directly above by the television camera 10 and is generated as a photographing signal representing a plane image of the object to be photographed, this photographing signal Is converted into a digital signal by the A / D converter 20.

When the computer program proceeds to step 120, the microcomputer 30 inputs and stores the digital signal from the AD converter 20 into the RAM of the image memory 50 as data representing the plane image (hereinafter referred to as plane image data). . When this input is complete, the microcomputer
30 determines in step 120a to be "YES", and in the next step 130, generates a binarization start signal necessary for starting the binarization circuit 40, and in response thereto, the binarization circuit. 40 is activated, the plane image data is read from the RAM of the image memory 50 and binarized, and the binarized result is data representing a binarized image F (see FIG. 3) (hereinafter, binarized image). Called data)
Is stored in advance in the RAM of the image memory 50.

In such a case, the binarization circuit 40 converts the planar image data into 1
Each pixel is read as serial data from the RAM of the image memory 50, and these serial data are sequentially binarized based on predetermined threshold data and stored in the RAM of the image memory 50. Further, in the binarized image F, the shaded area Fa is a light reflection portion (that is,
(White portion corresponding to “1”), and the non-hatched area Fb is
The non-light reflection part (namely, the black part corresponding to "0") in the said plane image is shown.

When the binarization by the binarization circuit 40 is completed, the microcomputer 30 generates a reduction activation signal necessary for activating the reduction circuit 60 in step 140, and in response thereto, the reduction circuit.
The data controller 61 of 60 is activated. Then, in step 140a, the microcomputer 30 causes the image memory 50
When the fill-in image data (see FIG. 4) is read from the ROM, the data controller 61 sequentially applies the fill-in image data for 9 pixels as serial data to the comparison circuit 63. Then, the comparison circuit 63 causes the data controller
Data representing the reduced image Ga (see FIG. 5A) by reducing the black portion by one pixel along the entire outer periphery of the filled image G in accordance with the respective serial data from 61 and the reduced logical data from the RAM 62 (see FIG. 5A). (Hereinafter referred to as reduced image data), and is stored in the image memory 50 via the data controller 61.
Store in RAM.

In such a case, in the reduced image Ga, the non-hatched area is
The reduced black portion corresponding to "0" is shown, and the shaded area is
A white portion corresponding to "1" is shown.

When the reduction circuit 60 completes the reduction, the microcomputer 30 determines “YES” in step 140b, and outputs the first matching activation signal required for activating the AND gate 72.
It occurs at 150. Then, the data controller 71
In response to the first matching activation signal from the microcomputer 30, the binarized image data (see FIG. 3) and the reduced image data (see FIG. 5 (A)) from the RAM of the image memory 50 for one pixel each. Each of them is sequentially read as serial data and given to the AND gate 72.

Then, the AND gate 72 sequentially calculates each logical product of each serial data in the binarized image data and each serial data in the reduced image data, and inputs it to the RAM of the image memory 50 via the data controller 71. In such a case, the entire outer peripheral edge of the non-hatched area Fb of the binarized image F (see FIG. 3) corresponds to the inside of the entire inner peripheral edge of the shaded area of the reduced image Ga (see FIG. 5A). The result of the AND operation by the AND gate 72, that is, the result of the matching by the AND gate 72 with respect to the binarized image data and the reduced image data is the data representing the matching image Gb as shown in FIG. 1 Matching image data)
Is stored in the RAM of the image memory 50. This allows
It can be seen that the matching image Gb is the same as the reduced image Ga.

When the matching by the AND gate 72 is completed, the microcomputer 30 determines “YES” in step 150a, and in step 160, generates the second matching activation signal necessary for activating the exclusive OR gate 73. Then, the data controller 71 causes the microcomputer 30
In response to the second matching activation signal from the image memory 50
Image data from ROM and RAM (see Fig. 4)
Then, the first matching image data (see FIG. 5B) is sequentially read out as serial data for each pixel and applied to the exclusive OR gate 73.

Then, the exclusive OR gate 73 sequentially calculates each exclusive OR of each serial data in the fill image data and each serial data in the first matching image data, and outputs each operation result as the second matching image data. The data is stored in the RAM of the image memory 50 via the data controller 71. When the calculation by the exclusive OR gate 73 is completed, the microcomputer 30 determines “YES” in step 160a, and advances the computer program to step 170. At this stage, it is determined that there is a mismatch on the assumption that a pixel portion corresponding to “1” exists in the second matching image data, that is, the filled image G (see FIG. 4) and the first matching image Gb. (See FIG. 5 (B)), in other words, it is determined that the second matching image data is not “0”, and the determination in step 170 is “NO”. .

In this way, when the determination in step 170 is “NO”, the microcomputer 30 generates a reduction start signal and starts the data controller 61 in step 140. Then, the microcomputer 30 executes step 140a.
When the first matching image data (see FIG. 5 (B)) is read from the RAM of the image memory 50 at
Reference numeral 61 sequentially applies the first matching image data to the comparison circuit 63 for each 9 pixels as serial data.

Then, the comparison circuit 63 reduces the black portion by one pixel along the entire outer periphery of the first matching image Gb according to each serial data from the data controller 61 and the reduction logical data from the RAM 62, and reduces the reduced image Gc (first Data controller formed as reduced image data representing FIG. 6 (A))
The image is stored in the RAM of the image memory 50 via 61. In such cases,
In the reduced image Gc, the non-hatched area indicates the reduced black portion corresponding to “0”, and the hatched area indicates the white portion corresponding to “1”.

Then, when the determination in step 140b is "YES", the microcomputer 30 generates the first matching start signal in step 150, and in response thereto, the data controller 71 outputs the binary value from the RAM of the image memory 50. The digitized image data (see FIG. 3) and the reduced image data (see FIG. 6 (A)) are sequentially read out as serial data for each one pixel and given to the AND gate 72.

Then, the AND gate 72 sequentially calculates each logical product of each serial data in the binarized image data and serial data in the reduced image data, and inputs it to the RAM of the image memory 50 via the data controller 71.

In such a case, the portion indicated by the symbol Pa in FIG. 3 in the non-hatched area Fb of the binarized image F (hereinafter referred to as the protruding portion Pa)
Corresponds to a part of the hatched area of the reduced image Gc, and the entire outer peripheral edge of the remaining area excluding the protruding portion Pa of the non-hatched area Fb is within the hatched area of the reduced image Gc (see FIG. 6A). Since it corresponds to the inside of the entire periphery, the matching result by the AND gate 72 is stored in the image memory 50 as the first matching image data representing the matching image Gd as shown in FIG. 6B.
Stored in RAM.

When the determination in step 150a is "YES", the microcomputer 30 generates a second matching activation signal in step 160, and in response thereto, the data controller 71.
However, each of the first matching image data (see FIG. 5 (B) and FIG. 6 (B)) from the RAM of the image memory 50 is 1
Each pixel is sequentially read out as serial data and given to the exclusive OR gate 73.

Then, the exclusive OR gate 73 sequentially calculates each exclusive OR of both serial data in both the first matching image data, and outputs each calculation result to the second.
The matching image data is input and stored in the RAM of the image memory 50 via the data controller 71. Step 160a
When the determination in step 1 is "YES", the microcomputer 30 determines "NO" in step 170 as described above. That is, the first matching image Gb (see FIG. 5 (B))
When there is a change between the first matching image Gd and the first matching image Gd (see FIG. 6B), in other words, it is determined that the second matching image data is not “0”.

Hereinafter, each step 140, 140a, 140b, 150, 150 as described above
In the process of repeating the cyclic operation of the computer program passing through a, 160, 160a and 170, the data representing the first matching image Gd (see FIG. 6B) is converted by the reduction circuit 60 in substantially the same manner as described above. , The reduced image Ge (see FIG. 7 (A)) is reduced, and the data representing the reduced image Ge is the binarized image F (third image).
(Refer to the drawing) and the data representing the first matching image Gf (see FIG. 7B) by the AND gate 72, and the data representing the first matching image Gf is reduced. Reduced image Gh by circuit 60
The AND gate 72 causes the first matching image Gi to be reduced between the data representing the reduced image Gh and the data representing the binarized image F while being reduced as the data representing (see FIG. 8A). Matching is performed as data representing (see FIG. 8B).

Further, in the same manner as described above, the data representing the first matching image Gi is reduced by the reducing circuit 60 as the data representing the reduced image Gj (see FIG. 9A), and the data representing the reduced image Gj. Is matched with the data representing the binarized image F by the AND gate 72 as data representing the first matching image Gk (see FIG. 9B), and represents the first matching image Gk. The data is reduced by the reduction circuit 60, and the reduced image Gl (Fig. 10 (A)).
The data representing the reduced image Gl and the data representing the binarized image F are reduced by the AND gate 72 to generate the first matching image Gm (FIG. 10 (B)). (Reference)).

Furthermore, in the same manner as described above, the first matching image
Data representing Gm is converted by the reduction circuit 60 into a reduced image Gn.
The AND gate 72 causes the first matching image Go to be reduced between the data representing the reduced image Gn and the data representing the binarized image F while being reduced as the data representing (see FIG. 11A). The data representing the first matching image Go is matched as the data representing (see FIG. 1 (B)), and the data representing the first matching image Go is reduced by the reducing circuit 60.
The data representing the reduced image Gp and the data representing the binarized image F are reduced by the AND gate 72 to generate the first matching image Gq (first image). 12 (see FIG. 12 (B)).

Thereafter, in the same manner as described above, the data representing the first matching image Gq is reduced by the reducing circuit 60 as the data representing the reduced image Gr (see FIG. 13 (A)), and the reduced image Gr is The represented data is matched with the data representing the binarized image F by the AND gate 72 as the data representing the first matching image Gs (see FIG. 13 (B)).

Then, after the determination of "YES" in step 150a, the microcomputer 30 generates the second matching start signal in step 160, and in response thereto, the data controller 71 has already stored in the RAM of the image memory 50. Each data representing both first matching images Gq, Gs (see FIG. 12 (B) and FIG. 13 (B)) is read out as serial data in the same manner as above, and the exclusive OR gate 73 excludes each serial data. The logical ORs are sequentially calculated and input and stored in the RAM of the image memory 50 via the data controller 71 as the second matching image data.

Then, when the determination in step 160a is "YES", the computer program proceeds to step 170. However, since the first matching images Gq and Gs match each other and the second matching image data is "0", that is, the second matching image data is all black, the microcomputer 30 causes the binary image F Based on the judgment that the shaded area Fc (see FIG. 3) in the non-shaded area Fb of No. has been filled, it is determined to be “YES” in step 170, and next step 17
At 0a, the data representing the first matching image Gs is converted into display data and generated as a display signal. Then, the CRT controller 80 causes the microcomputer 30 to generate the contents of the display signal as a video signal together with the synchronizing signal, and in response thereto, the CRT 90 causes the first matching image Gs, that is, the hatched area F to be displayed.
The binarized image F is displayed by blackening out c.

As described above, the binarization circuit 40, the reduction circuit 60, and the matching circuit 70 are configured by hardware, and only the minimum content such as the arithmetic processing content necessary for controlling the starting order of these circuits is software in the microcomputer 30. Since it is configured with the above, it is possible to utilize the synergistic effect of software and hardware without recognizing the fill area of the binarized image, and fill the fill area with a simple and versatile hardware configuration. Can be performed at high speed and at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the microcomputer in FIG. 1, FIG. 3 is an illustration of a binarized image, and FIG. 4 is a filled image. FIG. 5 (A) to FIG. 13 (B) are illustrative diagrams of reduction and matching. Explanation of Codes 10 ... Television camera (imaging means), 30 ... Microcomputer (arithmetic processing means), 40 ... Binarization circuit (binarization means), 50 ... Image memory, 60 ... Reduction circuit (reduction means),
70 ... Matching circuit (matching means).

Continued Front Page (56) References IEEE Transactions on Pattern Analysis and Machine Intelligenence, vol. PAMI-3, no. 4, 1981, p. 476-481, Kendall II Preston, Jr .: "Some Notes on Cellular Logic Operators".

Claims (1)

[Claims] 1. A photographing means for photographing a contour image of an object to be photographed, which is irradiated with light from an appropriate light source, as a plane image, and a plane image photographed by the photographing means is binarized and formed as a binarized image. Binarizing means for generating this binarized image as binarized image data, and a reference image having an outer contour capable of surrounding the outer contour of the plane image photographed by the photographing means as the reference image data. A reference image data generating unit, a reducing unit configured to reduce the black portion by one pixel along the entire outer circumference of the reference image generated by the reference image data generating unit to generate reduced image data, and the reducing unit First matching means for generating first matching image data by ANDing the generated reduced image data and the binarized image data generated by the binarizing means; Matching means including second matching means for generating second matching image data by exclusive OR of the first matching image data generated by the first matching means and the reference image data generated by the reference image data generating means. And an output unit that outputs the first matching image data, and an arithmetic process that uses the first matching image data generated by the first matching unit as new reference image data, and the new reference image. A calculation process for reducing by the reducing means to generate new reduced image data, and a new logical product by the first matching means of the reduced image data and the binarized image data generated by the binarizing means. Processing for generating such first matching image data, and the new first matching image data Performs an arithmetic processing to produce a new second matching image data by an exclusive OR by the second matching means between the new reference image data, the new second
The above-described arithmetic processes are repeatedly performed until the matching image data becomes all black, and when the new second matching image data becomes all black, the output means outputs the new first
An image processing apparatus characterized in that arithmetic processing means for outputting matching image data is provided.