JPH0759041B2 - Blanking circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the invention C Prior art (Fig. 4) D Problems to be solved by the invention (Fig. 4) E Means for solving problems (Figs. 1 and 3) ) F action (Figs. 1 and 3) G embodiment (Figs. 1 to 3) H Effect of the invention A Industrial field of application The present invention relates to a blanking circuit, and particularly to raster video signal processing of a video camera. It is suitable for application to circuits and the like.

B. SUMMARY OF THE INVENTION In the blanking circuit according to the present invention, a predetermined voltage is applied only during the blanking period and a voltage different from the blanking period is applied during the blanking period, so that the desired voltage is blanked regardless of the input signal waveform. The ranking operation can be performed.

C Conventional Technology Conventionally, for example, in a raster video signal processing circuit of a video camera or the like, an input signal waveform is replaced with a predetermined reference voltage, that is, a blanking voltage for a predetermined period, that is, a blanking period T _BL , as shown in FIG. By using such a blanking circuit, a blanking operation is performed to remove a noise part in the blanking period of the input signal and to create a reference point for signal processing such as γ correction.

In FIG. 4, the NPN transistor Q1 is a constant current source 2
The output signal of the signal source 1 connected to the input terminal T1 is output from the emitter through the resistor 3 to the base of the transistor Q2 by the buffer circuit using the.

NPN type transistors Q2 and Q3 are NAM with differential amplifier circuit configuration.
A (non addition mixing) circuit is configured with the constant current source 4, and the commonly connected emitters are led to the output terminal T0.

The base of the transistor Q3 is connected to a reference power source 6 having a positive voltage V ₀₁ , for example, while the base of the transistor Q2 and the connection midpoint of the resistor 3 are synchronized with the blanking pulse BL and the ground. A switch circuit 5 that short-circuits the line L2 is connected.

In the above configuration, the blanking period T of the input signal S1
_{During the BL} , when the switch circuit 5 is turned on by the control signal BL, the base voltage of the transistor Q2 is lowered, the transistor Q2 is turned off, and the transistor Q3 is turned on.

Therefore, the blanking voltage V ₀₁ -V _{BE3 of} a value obtained by subtracting the base emitter voltage V _BE3 of the transistor Q3 from the voltage V ₀₁ of the reference power supply 6 is output to the output terminal T0.

On the other hand, in the period T _S1 other than the blanking period T _BL , the base voltage V _B2 of the transistor Q2 becomes higher than the base voltage V _B3 of the transistor Q3, and the transistor Q2 turns on and the transistor Q3 turns off.

Therefore, the input signal S1 is applied to the output terminal T0 by the transistor Q1.
A voltage shifted by the base and emitter voltages V _BE1 and V _{BE2 of} Q2 and Q2 to the potential side of the ground line L2 is output.

Thus, during the blanking period T _BL , the input signal S
1 will be replaced with a noise-free clamp voltage that can be used as a reference point for signal processing in the subsequent circuit.

C The problem to be solved by the invention is, for example, in the case of performing a process for changing the gain of the amplifier according to the level of the input signal S1 like a γ correction circuit, the reference point of the operation is set as the input signal S1. It is desirable to handle the black level voltage as a reference.

That is, it is desirable to set the blanking voltage to the black level voltage of the input signal S1.

However, in the conventional blanking circuit of FIG. 4, when the base voltages V _B2 and V _B3 of the transistors Q2 and Q3 are made equal to make the voltages equal, the transistors Q2 and Q3 are both turned on and linearly operated. State, so that transistors Q2 and Q3 affect each other at voltages in the vicinity. As a result, blanking the ranking period T _BL, appears the effect of the waveform of the input signal S1, the influence of the current of the transistor Q3 to the input signal S1 appearing in a period T _S1 other than the blanking period T _BL.

Therefore, a noise component appears in the blanking period T _BL , or a signal near the black level changes.

In order to solve this problem, conventionally, the blanking voltage is selected to be about 50 to 100 [mV] lower than the black level voltage, and the difference voltage is taken into consideration in the subsequent circuit connected to the blanking circuit. Is adopted. However, in this case, the temperature drift of the difference voltage must be taken into consideration, and there is a problem that the configuration of the image signal processing circuit as a whole becomes complicated.

When the base voltage V _B2 of the transistor Q2 becomes lower than the base voltage V _{B3 of the} transistor Q3 in the period T _S1 other than the blanking period T _BL , the transistor Q2 replaces the base voltage V _B3 .
Since the transistor Q3 turns on, the output terminal T0
The blanking voltage V ₀₁ −V _BE3 will be output.

Therefore, since the waveform of the input signal S1 clamped by the blanking voltage V ₀₁ −V _BE3 is output, the blanking voltage V ₀₁ −V is set at the intermediate level included in the change width of the input signal S1. It was difficult to perform a blanking operation for a signal that requires setting _BE3 , for example, a color difference signal.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a blanking circuit capable of performing a blanking operation at a desired voltage regardless of the change width of an input signal.

E Means for Solving the Problems In order to solve the above problems, the present invention is a non-additive synthesis circuit combining a differential amplifier circuit and a constant current source, and is a blanking period T _BL of the input video signal S1. The DC voltage of the input video signal S1 is reduced (or increased) during a period corresponding to T1 and a video signal composed of T _S1 and the input video signal S1 is output during periods other than the period corresponding to the blanking period T _BL .
Circuit (Q4, Q5, 10 (Q10, Q14, Q15, 13)) and its first circuit (Q4, Q5, 10 (Q10, Q14, Q15, 13)) During the period corresponding to the blanking period T _BL , a predetermined reference voltage V ₀₂ is output, and during the period other than the period corresponding to the blanking period T _BL , T _S1 , the DC voltage of the reference voltage is decreased (or increased). A second circuit (Q6, Q7, 11 (Q11, Q16, Q17, 15)) that outputs the output, and a first and second circuit (Q4, Q5, 10 (Q10, Q14, Q15, 13)) and (Q6, Q7, 11 (Q11, Q16, Q17, 15)) The same non-additive synthesis circuit as the first circuit (Q4, Q5, 10 (Q10, Q1)
4, Q15, 13)) is compared with the video signal output from the second circuit (Q6, Q7, 11 (Q11, Q16, Q17, 15)) and the high voltage (or The third circuit that selectively outputs the lower one and (Q8, Q9, 12 (Q12, Q13, 1
4)) are provided, and the blanking period T _BL of the input video signal S1 is
_Is replaced with the reference voltage V ₀₂ to output the output video signal SO.

F-action First, second, and third circuits (Q4, Q5, 10 (Q10, Q
14, Q15, 13)), (Q6, Q7, 11 (Q11, Q16, Q17, 1
5)), (Q8, Q9, 12 (Q12, Q13, 14)), the input video signal S1 is the first circuit (Q4, Q5, 10 (Q10, Q14, Q1).
5, 13)), only the blanking period T _BL is clamped to a sufficiently low (or high) DC voltage. On the other hand, the reference voltage is the second circuit (Q6, Q7, 11 (Q11, Q16, Q17, 15))
Therefore, only the blanking period T _BL has a predetermined reference voltage V _02.
And T _S1 has a sufficiently low (or high) DC voltage during a period other than the blanking period T _BL . As a result, the third circuit (Q8, Q9, 12 (Q12, Q13, 14)) compares these, and selectively outputs the higher (or lower) voltage, so that the blanking period T of the input video signal S1 is _BL
It is possible to output the output video signal SO in which is replaced with the reference voltage V ₀₂ .

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 4 are given the same reference numerals, PNP transistors Q4 and Q5, PNP transistors Q6 and Q7, and NPN transistors Q8 and Q9 are used to collect collector and Three NAM circuits having a differential amplifier circuit configuration in which the emitters are connected to each other are formed.

The collectors of the transistors Q4 and Q5 are connected to the ground line L2, and the emitter is connected to the power supply line L1 via the constant current source 10. On the other hand, the input signal S1 of the signal source 1 is applied to the base of the transistor Q4, and the blanking pulse BL1 shown in FIG. 2B is input to the base of the transistor Q5.

Thus, if the base voltage V _{B5 of} transistor Q5 is lower than the base voltage V _{B4 of} transistor Q4, then transistor Q5
When Q5 is turned on and the transistor Q4 is turned off, the voltage of the emitters of the transistors Q4 and Q5 becomes the voltage V _B5 + V _BE5 obtained by adding the base emitter voltage V _BE5 of the transistor Q5 to the base voltage of the transistor Q5.

Conversely, if the base voltage V _B4 of transistor Q4 is lower than the base voltage V _{B5 of} transistor Q5, then transistor Q4
Turns on and transistor Q5 turns off,
The voltage across the transistors Q4 and Q5 is V _B4 + V _BE4 , which is the base voltage V _B4 of the transistor Q4 plus the base emitter voltage V _BE4 of the transistor Q4.

The collectors of transistors Q6 and Q7 are ground line L2.
Connected to the power supply line via the constant current source 11.
It is connected to L1. The base of the transistor Q7 is connected to the reference power source 9 having a positive voltage V ₀₂ that determines the output voltage in the blanking period, and the base of the transistor Q6 is shown in FIG. Blanking pulse BL2 is input.

Thus, transistors Q6 and Q7 are connected to transistors Q4 and
Operates similarly to Q5, with the base voltage V _{B6 of} transistor Q6
Is lower than the base voltage V _B7 of the transistor Q7, the transistor Q6 is turned on and the emitter voltage of the transistors Q6 and Q7 is the base voltage V _B6 of the transistor Q6 plus the base emitter voltage V _BE6 of the transistor Q6. Voltage
It becomes V _B6 + V _BE6 .

Conversely, the base voltage V _B7 of transistor Q7 is
When the voltage is lower than the base voltage V _B6 of the transistor Q7, the transistor Q7 is turned on and the base voltage V _B7 of the transistor Q7 is added to the base emitter voltage V _BE7 of the transistor Q7 to obtain the voltage V _B7 + V
_BE7 .

Further, the collectors of the transistors Q8 and Q9 are the power line L1.
And the emitter is connected to the ground line L2 via the low current source 12. The base of the transistor Q8 is connected to the emitters of the transistors Q4 and Q5, and the base terminal of the transistor Q9 is connected to the emitters of the transistors Q6 and Q7.

The emitters of the transistors Q8 and Q9 are led to the output terminal T0.

Thus, transistors Q8 and Q9 are transistors Q8 and Q9 when the base voltage V _{B8 of} transistor Q8 (ie, the emitter voltage of transistors Q4 and Q5) is higher than the base voltage V _{B9 of} transistor Q9 (ie, the emitter voltage of transistors Q6 and Q7). When Q8 is turned on, the voltage V _B8 −V _{BE8 obtained} by subtracting the base emitter voltage V _BE8 of the transistor Q8 from the base voltage V _B8 of the transistor Q8 is output to the output terminal T0.

Conversely, the base voltage V _B9 of the transistor Q9 is the transistor QR.
If it is higher than the base voltage V _B8 of the transistor Q9, the transistor Q9 is turned on, and the voltage V _{BE9 obtained} by subtracting the base emitter voltage V _BE9 of the transistor Q9 from the base voltage V _B9 of the transistor Q9.
Outputs _B9 −V _BE9 .

Blanking pulse BL1, as shown in FIG. 2 (B), the blanking period T _BL at 0 [V] (the input signal S
Becomes a voltage lower than 1), the blanking period T in a period T _S1 other than _BL, a voltage higher than the voltage of the input signal S1 V _BL1
become.

The blanking pulse BL2 is, as shown in FIG. 2 (C), the voltage V of the reference power source 9 during the blanking period T _BL .
_The voltage becomes V _BL2 higher than ₀₂ , and the voltage becomes 0 [V] in the period T _S1 other than the blanking period T _BL .

In the above configuration, during the blanking period T _BL , the transistor Q5 is turned on when the blanking pulse BL1 (FIG. 2 (B)) falls to 0 [V]. At this time, the base voltage V _B8 of the transistor Q8 is the base-emitter voltage V _B of the transistor Q5.
_BE5 (≈ V _BE ) (Fig. 2 (D)). On the other hand, during the blanking period T _BL , the transistor Q7 is turned on by the blanking pulse BL2 (FIG. 2 (C)) rising to the voltage V _BL2, and the base voltage of the transistor Q9.
V _B9 is the base emitter voltage V of transistor Q7
_{The sum of BE9} (≈V _BE ) and voltage V _{02 results} in voltage V ₀₂ + V _BE (Fig. 2 (E)).

Therefore, in the blanking period T _BL , the transistor Q
The relationship between the base voltages V _B8 and V _B9 of 8 and Q9 is as follows: V _B9 = V ₀₂ + V _BE > V _BE = V _B8 (1), the transistor Q9 is turned on, and the output terminal
T0 is the voltage obtained by subtracting the base-emitter voltage V _BE (≈ V _BE ) of the transistor Q9 from the base voltage V _B9 of the transistor Q9, that is, V _B9 −V _BE9 ≈ V ₀₂ (2) (Fig. 2). (F)).

On the other hand, in the period T _S1 other than the blanking period T _BL , the blanking pulse BL1 becomes the voltage V _BL1 (second
(B)), and the blanking pulse BL2 has a voltage of 0
Since it becomes [V], the transistors Q4 and Q6 are turned on. At this time, the base voltage V _B8 of the transistor Q8 becomes the voltage of the input signal shifted to the positive side by the base / emitter voltage V _BE4 (≈V _BE ) of the transistor Q4, as shown in FIG. Base voltage V of transistor Q9
_As shown in FIG. 2 (E), _B9 becomes the base-emitter voltage V _BE6 (≈V _BE ) of the transistor Q6.

Therefore, the relation between the base voltages V _B8 and V _B9 of the transistors Q8 and Q9 is as follows: V _B8 > V _B9 = V _BE (3) As a result, the transistor Q8 is turned on and the input signal is applied to the output terminal T0. The voltage of S1 is obtained (Fig. 2 (F)).

Thus, the voltage V ₀₂ of the reference power supply 9 is obtained at the output terminal T0 in the blanking period T _BL , and the waveform of the input signal S1 is obtained in the period T _S1 other than the blanking period T _BL. Become.

According to the above configuration, the voltage corresponding to the blanking voltage can be replaced during the blanking period T _BL , so that for the input signal S1 (for example, color difference signal) having an arbitrary waveform as necessary. It is possible to obtain a blanking circuit that can set the voltage V ₀₂ in the blanking period T _BL to an arbitrary value, for example, a black level.

Incidentally, in the case of the above embodiment, the voltage V ₀₂ of the blanking period T _BL
Can be set in a wide range from a value near the voltage V _CC -V _BE obtained by subtracting the base-emitter voltage V _BE7 of the transistor Q7 from the voltage V _CC of the power supply line L to a value near 0 [V].

FIG. 3 shows a second embodiment of the present invention. As shown by attaching the same reference numerals to corresponding portions with FIG. 1, NPN type transistors Q12 and Q13, Q14 and Q15, Q16 and Q17 are shown. NAM circuit consisting of three differential amplifier circuits, transistor Q10
And Q11 form a blanking circuit.

The collector of the transistor Q14 and Q15 are of the resistance value R ₂ resistor
The emitters are connected to each other via 16, and the emitter is connected to the ground line L2 via the constant current source 13 in common. Blanking pulses BL1 and BL2 are applied to the bases of the transistors Q14 and Q15, respectively.

The collector of the transistor Q14 receives the input signal S1 of the signal source 1 at its base and the power line L via the transistor Q10.
Connected to 1, the collector of transistor Q15 is connected to the base of transistor Q12.

Therefore, when the base voltage V _B14 of the transistor Q14 becomes higher than the base voltage V _B15 of the transistor Q15, the transistor Q14 is turned on and the base voltage V _{B of} the transistor Q12 is turned on.
_B12 becomes equal to the emitter voltage V _E10 of transistor Q10.

Conversely, the base voltage V _B15 of transistor Q14 is
_Below the base voltage V _{B15 of} 15, transistor Q15
Turns on, and the base voltage V
_B12 is a voltage drop caused by the current I ₁₃ of the constant current source 13 flowing through the resistor 16 V ₁₆ = I ₁₃ · R ₂
The voltage is lower than the emitter voltage V _{E10 of} .

Further, the collectors of the transistors Q16 and Q17 are connected to each other via the resistor 17 having the resistance value R ₃ , and the emitter is connected to the ground line L2 via the low current source 15 in common. Blanking pulses BL1 and BL2 are applied to the bases of the transistors Q16 and Q17, respectively.

The collector of the transistor Q16 and the base of the transistor Q13 are connected to the power supply line L1 via the transistor Q11 that receives the output voltage V ₀₃ of the reference power supply 20 at its base.

Therefore, when the base voltage V _{B16 of the} transistor Q16 becomes lower than the base voltage V _B17 of the transistor Q17, the transistor Q17 is turned on and the base voltage V _{B of} the transistor Q13 is
_B13 becomes equal to the emitter voltage V _{E10 of} transistor Q11.

Conversely, the base voltage V _B16 of transistor Q16 is
_Above the base voltage V _{B17 of 17} , transistor Q16
Turns on, and the base voltage V of the transistor Q13
_B13 becomes a voltage lower than the emitter voltage V _{E11 of the} transistor Q11 by a potential difference V ₁₇ = I ₁₅ · R ₃ generated by the current I ₁₅ of the constant current source 15 flowing through the resistor 17.

Further, the collectors of the transistors Q12 and Q13 are connected to the power supply line L1, and the emitter is connected to the ground line L2 via the constant current source 14 in common. And the transistor
The emitters of Q12 and Q13 are led to the output terminal T0.

Therefore, when the base voltage V _{B12 of the} transistor Q12 becomes higher than the base voltage V _{B13 of the} transistor Q13, the transistor Q12
12 turns on, and the base voltage V _{B12 of} transistor Q12
To base-emitter voltage V _BE12 lower voltage V _B12 −V
_BE12 is output to the output terminal T0.

Conversely, the base voltage V _B12 of transistor Q12 is
_Below the base voltage V _{B13 of} 13, transistor Q13
Turns on, and the voltage between the base voltage V _B13 of the transistor Q13 and the base-emitter voltage V _{BE13 is} lower than the voltage V _B13 −V _BE13.
Is output to the output terminal T0.

In the above configuration, since the voltage of the blanking pulse BL1 becomes lower than the voltage of the blanking pulse BL2 during the blanking period T _BL , the transistors Q15 and Q17 are turned on.

At this time, the base voltage V _B12 descent of the base emitter voltage V _BE10 and resistor 16 of the transistor Q10 from the voltage V _S1 of the input signal S1 Voltage I _13-R only the sum of the ₂ low voltage V _S1 -V _BE10 of the transistor Q12 - It becomes I ₁₂ · R ₂ .

Further, the base voltage V _B1 of the transistor Q13 is from the voltage V ₀₃ of the reference power source 20 to the base-emitter voltage V V of the transistor Q11.
Only _{BE11 has a} lower voltage V ₀₃ −V _BE11 .

The voltage V _S1 now the input signal S1, the voltage of the reference power supply 20 V
_{If 03} is selected so as to _{satisfy the} following expression V _S1 −V _BE10 −I ₁₂ · R ₂ <V ₀₃ −V _BE11 (3), the transistor Q13 will be turned on and output to the output terminal T0. the output signal S0 is comprised of the following equation _{S0 = V 03 -V BE11 -V BE13} ≒ V 03 -2V bE ...... (4).

On the other hand, during the period T _S1 other than the blanking period T _BL , the voltage of the blanking pulse BL1 becomes higher than the voltage of the blanking pulse BL2, so that the transistors Q14 and Q16 are turned on.

At this time, the base voltage V _B12 of the transistor Q12 is composed of a voltage V _S1 of the input signal S1 and the base emitter voltage V _BE10 only low voltage V _S1 -V _BE10 of the transistor Q10.

Further, the base voltage V _B13 of the transistor Q13 is from the voltage V ₀₃ of the reference power source 20 to the voltage V E between the base and emitter of the transistor Q11.
_BE11 and resistor 17 voltage drop voltage I ₁₅ · R ₃ lower voltage V
₀₃ −V _BE11 −I ₁₅ · R ₃

Here, within the range where the relationship of V _S1 −V _BE10 > V ₀₃ −V _BE11 −I ₁₅ · R ₃ (5) holds, the transistor Q12 turns on and the output signal S0 obtained at the output terminal T0. will _{S0 = V S1 -V BE10 -V BE12} ≒ V S1 -2V bE ...... (6).

Thus, in the blanking period T _BL , the voltage V ₀₃ −2V _BE based on the reference power source 20 is output. Blanking period T
During period T _S1 other than _BL , voltage V _S1 −
2V _BE will be output.

According to the above configuration, the range satisfying the formulas (3) and (5), that is, the following formula V ₀₃ −I ₁₅ · R ₃ <V _S1 <V ₀₃ + I ₁₂ · R ₂ (7) Within the range of satisfaction, the same effect as that of the first embodiment can be obtained.

Further, in the case of the present embodiment, since the NPN type transistor is used in all cases, it is possible to obtain a blanking circuit suitable for an IC.

An equivalent result can be obtained by performing a circuit configuration using an NPN transistor instead of the PNP transistor used in the above-described embodiment and using a PNP transistor instead of the NPN transistor.

In this case, the terminal voltage of each transistor, the blanking pulses BL1 and BL2, and the power supply voltage are inverted between positive and negative in this embodiment. For example, in the transistors corresponding to the transistors Q8 and Q9 in FIG. Means that the voltage on the input signal side increases and the voltage on the reference power source side decreases.

The present invention is not limited to the raster video signal processing circuit of a video camera, but can be widely applied as a blanking circuit of a signal processing circuit such as a television receiver and a video tape recorder.

H Effect of the Invention As described above, according to the present invention, by changing the input signal and the reference voltage level applied to the transistors forming the output differential amplifier circuit during the blanking period and other periods, Since the blanking voltage can be freely selected regardless of the waveform, it is possible to reliably insert a blanking section having an arbitrary voltage level that does not include noise in the raster video signal.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a first embodiment of a blanking circuit of the present invention, and FIG. 2 is a signal waveform diagram showing signals of respective parts thereof,
FIG. 3 is a connection diagram showing a second embodiment of the blanking circuit of the present invention, and FIG. 4 is a connection diagram showing a conventional circuit. 1 …… Signal source, 2,4,10 ～ 15 …… Constant current source, 3,16,17 ……
Resistors, 6, 9, 20 ... Reference power supply, Q1-Q17 ... Transistors.

Claims (1)

[Claims] 1. A non-additive synthesis circuit in which a differential amplifier circuit and a constant current source are combined, and the DC voltage of the input video signal is lowered (or raised) during a period corresponding to the blanking period of the input video signal. During the period other than the period corresponding to the blanking period, the first circuit that outputs the video signal composed of the input video signal and the non-additive synthesis circuit similar to the first circuit are used. A second circuit that outputs a predetermined reference voltage during a period corresponding to, and reduces (or increases) the DC voltage of the reference voltage and outputs during a period other than the period corresponding to the blanking period. It is a non-additive synthesis circuit similar to the first and second circuits, and compares the video signal output from the first circuit with the reference voltage output from the second circuit to obtain a high (or low) voltage. ) Is selected and output Comprising a third circuit, a blanking circuit for blanking period of the input video signal, characterized in that so as to deliver an output video signal by replacing the above reference voltage.