JPH0783438B2 - Video amplifier circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image amplification circuit used in a video camera or the like.

2. Description of the Related Art A video camera has a function of making an image positive or negative. Further, a gain adjusting function for setting the gain of the image is also provided. Furthermore, the function of inserting a character in the video is added. In these cases, conventionally, a plurality of amplifier circuits are provided in the video signal processing system, and the above functions are shared by the amplifier circuits. Incidentally, these amplifier circuits are usually formed by ICs.

SUMMARY OF THE INVENTION However, such a circuit has a drawback in that the number of amplifier circuits is large and the overall structure is complicated and large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a novel video amplifier circuit in which the amplifier circuit is small in scale and has various functions.

Means for Solving the Problems In order to achieve the above object, according to the present invention, input video signals are output in opposite phases to the output terminals of the first and second transistors that form a differential pair, and the first transistor of the first transistor is output. Of the third and fourth transistors whose input terminals are commonly connected to the output terminal and the fifth and sixth transistors whose input terminals are commonly connected to the output terminal of the second transistor, at least the third transistor
A video amplifier circuit comprising a double-balanced differential amplifier in which an amplified output is taken out from a commonly connected output terminal of a fifth transistor or a commonly connected output terminal of fourth and sixth transistors, Connected to the bases of the fourth, fifth, and sixth transistors are a first switching element connected to a circuit that generates a positive / negative switching voltage for video and a second switching element connected to a gain control voltage generation circuit. , O of the first and second switching elements depending on the positive / negative switching voltage
The configuration is such that N, OFF and ON, OFF of the third, fourth, fifth and sixth transistors are controlled.

Operation With such a configuration, only one double-balanced differential amplifier, which is the core of the video amplification circuit, is sufficient, and the third to sixth transistors that are included in this single double-balanced differential amplifier are turned on and off. The output signal and output terminal are only controlled by their respective functions to perform gain adjustment of the video signal, switching between positive and negative, compensation of change in DC output component due to gain adjustment of the video signal, insertion of a character signal, and the like.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (I) is the first and second transistors (Q ₁ ) (Q ₂ ), the resistor (R ₁ ), the constant current source (I) that form the lower differential pair to which the video signal (Y) is input. ₁ ) (I ₂ ), the third and fourth emitters commonly connected to the collector of the first transistor (Q ₁ ).
Transistor (Q ₃ ) (Q ₄ ) and second transistor (Q ₂ )
Of the fifth and sixth transistors (Q ₅ ) (Q ₆ ) whose emitters are commonly connected to the collector of and one end of which is commonly connected to the collectors of the fourth and sixth transistors (Q ₄ ) (Q ₆ ) Is a first block that constitutes a double-balanced differential amplifier from a load resistance (R ₂ ) connected to the source voltage line (1).

(II) is the 7th and 8th transistors (Q ₇ ) that form a differential pair
(Q ₈ ) and a constant current source (I ₈ ), the second block having the collector of the eighth transistor (Q ₈ ) connected to the load resistor (R ₂ ). The second block (II) plays a role of compensating for the change in the DC potential at the output point (a) when the gain is adjusted in the first block (I) to make a constant DC potential.

(III) is a third block forming part of the character DC gain supply circuit, made from 9 are differentially connected, the tenth transistor (Q ₉₎ and (Q ₁₀₎ and the constant current source (I ₁₀₎ The collector of the tenth transistor (I ₁₀ ) is connected to the output point (a). Thus, the second and third blocks (II) and (III) share the load resistance (R ₂ ) of the first block (I) as their output resistance.

Predetermined circuits are connected to the bases of the differential pair transistors forming the blocks (I), (II), and (III) via diodes. First, third forming over stage differential pair of the first block (I), the fourth transistor (Q ₃₎ (Q ₄₎ and fifth, the base of the sixth transistor (Q ₅₎ (Q ₆₎ Positive / The output terminals of the negative comparator (2) and the video signal gain adjustment voltage comparator (3) are connected via a diode, and a character comparator is provided at the bases of the fourth and sixth transistors (Q ₄ ) (Q ₆ ). The output terminal (4) is also connected via a diode. That is, the first terminal of the positive / negative comparator (hereinafter referred to as "P / N comparator") (2) (2a) is connected via a diode (D ₁₎ to the base of the third transistor (Q ₃₎ In addition, the first terminal (3a) of the gain adjustment voltage comparator (3) is connected via the PNP transistor (Q ₁₁ ) and the diode (D ₂ ). The second terminal (2b) of the P / N comparator (2) is connected to the base of the fifth transistor (Q ₅ ) through the diode (D ₄ ) and the first terminal (3a) of the gain adjustment voltage comparator (3). Are connected via a PNP transistor (Q ₁₁ ) and a diode (D ₃ ), respectively.

Next, the second terminal (2b) of the P / N comparator (2) is connected to the base of the fourth transistor (Q ₄ ) via the diode (D ₅ ) and the gain adjustment voltage comparator (3) is connected. The second terminal (3b) is connected via a PNP transistor (Q ₁₂ ) and a diode (D ₆ )
The second terminal (4b) of the comparator (4) is connected via the diode (D ₇ ). The first terminal of the base of the eighth transistor (Q ₈₎ P / N comparator (2) (2a) via the diode (D _8), also the gain adjustment voltage second terminal of the comparator (3) (3b) Are connected to the NPN transistor (Q ₁₂ ) via the diode (D ₉ ), and the second terminal (4 b) of the character comparator (4) is connected to the second terminal (4 b) via the diode (D ₁₀ ).

These diodes (D ₁ ) to (D ₁₀ ) are all configured as switching diodes together with diodes (D ₁₁ ) to (Q ₁₅ ) described later. Diodes (D ₁ ) to (D ₄ )
, And the diodes (D ₅ ) to (D ₁₀ ) have opposite polarities with respect to the bases of the transistors (Q ₃ ) to (Q ₆ ). Correspondingly, a constant current source (I ₂ ) (I ₄ ) whose one end is connected to the connection potential point is connected to the bases of the third and fifth transistors (Q ₃ ) to (Q ₅ ). , While the fourth,
Constant current sources (I ₅ ) (I ₆ ) each having one end connected to the power supply voltage line (1) are connected to the bases of the sixth transistors (Q ₄ ) (Q ₆ ).

The P / N comparator (2) compares the reference voltage obtained by dividing the source voltage (+ Vcc) with the resistors (R ₄ ) and (R ₅ ) and the output of the P / N switch (6). Then, when the P / N switch (6) is set to the contact (P) side in the positive mode, a positive voltage is output to the first terminal (2a) and a negative voltage is output to the second terminal (2b). Output. Conversely, when the P / N switch (6) is set to the contact (N) side in the negative mode, a negative voltage is generated at the first terminal (2a) and a positive voltage is generated at the second terminal (2b). The blanking pulse (7) is further input to the P / N comparator (2) through the diode (D ₁₆ ). This is no problem in the positive case, but up to the sync signal part in the video signal in the negative case. If it is also inverted, it becomes impossible to synchronize in the subsequent circuit, so as a countermeasure against this, the negative diving is forcibly canceled (and therefore made positive) during the horizontal blanking and vertical blanking periods. .

The gain adjustment voltage comparator (3) is connected to the power supply voltage (+ Vc
The reference voltage obtained by dividing c) by resistors (R ₇ ) (R ₈ ) and the voltage adjusted and set by the variable resistor (VR ₁ ) are compared, and the DC voltage corresponding to the difference is calculated as the first and second Output to terminals (3a) and (3b) with opposite polarities. Transistor (Q ₁₁ ) (Q ₁₂ )
Constant current sources (I ₁₂ ) (I ₁₃ ) (I ₁₄ ) are connected to (Q ₁₃ ) as shown. The character comparator (4) compares the character input (8) with the reference voltage obtained by dividing the power supply voltage (+ Vcc) with the resistors (R ₉ ) and (R ₁₀ ), and the first and second terminals (4a) (4a) 4b) are output with opposite polarities respectively. When there is a character input (8), a high level is output to the first terminal (4a), a low level is output to the second terminal (4b), and when there is no character input (8). Low level on the first terminal (4a),
It outputs a high level to the second terminal (4b). The character input and the video output are shown in FIGS.

Next, regarding the second block (II), the second terminal (3b) of the gain adjustment voltage comparator (3) is connected to the base of the seventh transistor (Q ₇ ) via the NPN transistor (Q ₁₂ ) and the diode (D ₁₁ ). in, also the first terminal (3a) is connected to the base of the eighth transistor via the NPN transistor (Q ₁₃₎ and the diode _{(D 12) (Q 8)} . Character comparator (4) at the base of the 8th transistor (Q)
The second terminal (4b) of is also connected via the diode (D ₁₃ ). Constant current sources (I ₇ ) (I ₉ ) are further connected to the bases of the seventh and eighth transistors (Q ₇ ) (Q ₈ ) as shown.

The ninth transistor (Q
The base ₉₎ is connected characters gain adjustment voltage comparator (5) second terminal (5b) is directly, whereas the base of the tenth transistor (Q ₁₀₎ a first terminal (4a character comparator (4) ) Is connected via a diode (D ₁₄ ) and the first terminal (5a) of the character gain adjustment voltage comparator (5) is connected via a transistor (Q ₁₄ ) and a diode (D ₁₅ ). (VR ₂ ) is a variable resistor for adjustment.

Next, the operation of FIG. 1 will be described. First, when there is no character input (8) and in the positive mode, the second terminal (4b) of the character comparator (4) becomes high level, so the diodes (D ₇ ) (D ₁₀ ) (D ₁₃ ) are OFF, On the other hand, since the first terminal (4a) becomes low level, the diode (D ₁₄ ) turns on. As a result, the third block (III)
Turns off the transistor (Q ₁₀ ) and is essentially inactive. Now that the positive mode is set, the diode (D ₁ ) is turned on in the first block (I) by the positive voltage of the first terminal (2a) of the P / N comparator (2) to turn the third voltage on.
When the transistor (Q ₃ ) turns on, the diode (D ₂ )
Turns off. Further, the diode (D ₈ ) is turned off by the positive voltage of the first terminal (2a). Therefore, the sixth transistor (Q ₆ ) is turned on. On the other hand, P / N comparator (2) a negative voltage by the diode of the second terminal of (2b) (D ₄₎ become OFF, the thus Daido (D ₃₎ is in the ON, the fifth transistor (Q ₅₎ also with ON Become. The fourth transistor (Q ₄ ) is turned off because the diode (D ₅ ) is turned on by the negative voltage of the second terminal (2b). Since the fourth transistor (Q ₄ ) is OFF, the first transistor (Q ₄ )
The negative video signal from ₁ ) does not appear at the output point (a), but instead the positive video signal from the second transistor (Q ₂ ) is obtained at the output point (a) through the sixth transistor (Q ₆ ). At that time, since the 5th and 6th transistors (Q ₅ ) (Q ₆ ) are receiving the DC voltage from the gain adjustment voltage comparator (3), the output video signal is set by the variable resistor (VR ₁ ). It will be according to the gain. The DC potential at the output point (a) varies depending on the gain setting by the variable resistor (VR ₁ ). However, this fluctuation is compensated by the output of the eighth transistor (Q ₈ ) of the second block (II). This is because the fifth and sixth transistors (Q ₅ ) (Q ₆ ) of the first block (I) and the second and sixth transistors (Q ₆ ) of the second block (II).
It can be also understood that the seventh and eighth transistors (Q ₇ ) (Q ₈ ) are configured to be subjected to reverse gain control by the output of the gain adjustment voltage comparator (3). Thus, the fact that the DC potential at the output point (a) is maintained at a constant value is due to the fact that a subsequent circuit (not shown) is directly connected to the output point (a) (DC coupling) (in most cases in an IC, It is possible to enjoy the advantage of not directly impairing the bias state of the subsequent circuit by directly connecting it to the next stage.

Next, in the positive mode described above, when the character input (8) is given as shown in FIG.
During this character input, the output levels of the first and second terminals (4a) and (4b) of the character comparator (4) are inverted, the first terminal (4a) is at the high level and the second terminal (4b) is Since it becomes low level, the diode (D ₇ ) (D ₁₀ ) and the diode (D ₁₃ ) connected to the second terminal (4b) are turned on, and the 4th, 8th and 10th transistors (Q ₄ ) (Q ₄ ) (Q ₄ ) ₈ ) (Q ₁₀ ) is also O
It will be FF. Therefore, in the first block (I), only the third and fifth transistors (Q ₃ ) (Q ₅ ) are turned on,
No video signal is derived at the output point (a). In addition, the second block (II) is substantially deactivated by turning off the eighth transistor (Q ₈ ). However, the diode (D) connected to the first terminal (4a) of the character comparator (4)
₁₄ ) is turned off, so the 10th transistor (Q ₁₀ ) of the 3rd block (III) is turned on and the current of the gain corresponding to the output of the character gain adjustment voltage comparator (5) flows through the load resistance (R ₂ ). Therefore, the character output occurs at the output point (a) with a desired output size. When the character input (8) ends, the original state is restored, and the positive output of the video signal (Y) and the output of the second block (II) are given to the output point (a).

Next, when the switch (6) is set to the contact (N) side and the negative mode is set, the first terminal (2a) of the P / N comparator (2) becomes a negative voltage and the second terminal (2b) becomes a positive voltage. , In the first block (I), the diode (D ₁ ) is off, the diode (D ₂ ) is on, the third transistor (Q ₃ ) is on, and the diode (D ₅ ) is off and the fourth transistor (Q ₄ ) is on. ) Is ON
It becomes a state. On the other hand, the diode (D ₄ ) is turned on, the diode (D ₃ ) is turned off, and the fifth transistor (Q ₅ ) is turned on, but the sixth transistor (Q ₆ ) is turned on by the eighth diode (D ₈ ).
Since it is turned on, it is turned off, and in the end, the first block (I) receives the fourth negative image signal from the first transistor (Q ₁ ).
It will occur at the output point (a) through the transistor (Q ₄ ). Other gain control operation, 2nd block (I
The operations of I) and the third block (III) are performed according to the operation in the positive mode described above.

EFFECTS OF THE INVENTION As described above, according to the present invention, the positive / negative is provided via the first switching element to the bases of the third to sixth transistors forming the upper stage differential pair of the double balance type differential amplifier for amplifying the video signal. A switching voltage generating circuit is connected and a control voltage generating circuit is connected via a second switching element, and the positive / negative switching voltage turns ON / OFF the first and second switching elements,
Since the ON / OFF of the sixth transistor is controlled, there is an effect that only one double balance type differential amplifier is required and the circuit configuration is simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a video signal amplifier circuit embodying the present invention, and FIG. 2 is a signal waveform diagram thereof. (Q ₁ ) to (Q ₆ ) …… first to sixth transistors, (a) …… output point, (D ₁ ) (D ₄ ) (D ₅ ) (D ₈ ) …… first switching diode, ( D ₂ ) (D ₃ ) (D ₆ ) (D ₉ ) …… Second switching diode, (D ₇ ) (D ₁₀ ) …… Third switching diode, (II) …… Second block (compensation circuit), (III) ... 3rd block (character DC gain supply circuit), (2) ... positive / negative comparator, (3) ... gain adjustment voltage comparator, (5) ... character adjustment voltage comparator, (6) …… Positive / negative switch, (8) …… Character input.

Claims (1)

[Claims] 1. An input video signal is output to the output terminals of first and second transistors forming a differential pair in opposite phases to each other, and an input terminal is commonly connected to the output terminal of the first transistor. Of the fifth and sixth transistors whose input terminals are commonly connected to the output terminal of the fourth transistor and the second transistor, at least the output terminals of the third and fifth transistors connected in common or the fourth and sixth output terminals. In a video amplifier circuit comprising a double-balanced differential amplifier in which an amplified output is taken out from a commonly connected output terminal of transistors, a video positive circuit is provided at the bases of the third, fourth, fifth and sixth transistors. / Connecting a first switching element connected to a circuit for generating a negative switching voltage and a second switching element connected to a gain control voltage generating circuit,
According to the positive / negative switching voltage, the first
An image amplification circuit characterized in that the ON / OFF of the first and second switching elements and the ON / OFF of the third, fourth, fifth and sixth transistors are controlled.