JPH0760803B2 - Method for manufacturing semiconductor wafer - Google Patents
Method for manufacturing semiconductor waferInfo
- Publication number
- JPH0760803B2 JPH0760803B2 JP62139365A JP13936587A JPH0760803B2 JP H0760803 B2 JPH0760803 B2 JP H0760803B2 JP 62139365 A JP62139365 A JP 62139365A JP 13936587 A JP13936587 A JP 13936587A JP H0760803 B2 JPH0760803 B2 JP H0760803B2
- Authority
- JP
- Japan
- Prior art keywords
- gas
- flow passage
- main surfaces
- reaction tube
- gas flow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 34
- 150000001875 compounds Chemical class 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 239000002994 raw material Substances 0.000 claims description 7
- 239000007789 gas Substances 0.000 description 32
- 235000012431 wafers Nutrition 0.000 description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、Si基板にこれとは異種結晶構造を有する化合
物半導体をエピタキシャル成長させる半導体ウエハの製
造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor wafer, in which a compound semiconductor having a heterogeneous crystal structure is epitaxially grown on a Si substrate.
[従来の技術] Si基板にGaAs等の化合物半導体をエピタキシャル成長さ
せることは、有機金属化学気相成長(MOCVD)法や分子
線エピタキシー(MBE)法を用いて行われている。[Prior Art] Epitaxial growth of a compound semiconductor such as GaAs on a Si substrate is performed by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
しかし、これらは全てSi基板の片主面に対してエピタキ
シャル成長されている。ところが、SiとGaAs等の化合物
半導体は熱膨脹係数が異なるため、エピタキシャルウエ
ハにそりやクラックが生じてしまうという問題があっ
た。このクラックは勿論、若干のそりもデバイス作成プ
ロセスにおいては重要な障害となり、早急な解決策が必
要であった。However, these are all epitaxially grown on one main surface of the Si substrate. However, since the compound semiconductors such as Si and GaAs have different thermal expansion coefficients, there is a problem that the epitaxial wafer is warped or cracked. These cracks and, of course, some warpage became an important obstacle in the device manufacturing process, and an urgent solution was required.
そこで、Si基板の一端を反応炉中で支持し、Si基板の両
主面を均等に加熱しながら前記反応炉中に原料ガスを供
給し、少なくとも一層以上の同厚かつ同材質の化合物半
導体層を前記Si基板の両主面に同時にエピタキシャル成
長させる半導体ウエハの製造方法が提案されている(例
えば、特開昭62−101024号公報)。Therefore, one end of the Si substrate is supported in the reaction furnace, and the source gas is supplied into the reaction furnace while uniformly heating both main surfaces of the Si substrate, and at least one or more compound semiconductor layers of the same thickness and the same material are provided. There has been proposed a method for manufacturing a semiconductor wafer in which the Si is simultaneously epitaxially grown on both main surfaces of the Si substrate (for example, Japanese Patent Laid-Open No. 62-101024).
第1図はSi基板の両主面に化合物半導体層を形成した半
導体ウエハを示す説明図であり、Si基板2の鏡面加工さ
れた両主面には同厚かつ同材質の化合物半導体層3,3例
えばGaAs,GaAsP,GaAlAs等のエピタキシャル成長層が形
成されている。この化合物半導体層3,3は以下に説明す
る製造方法により、同時にSi基板2の両主面に成長され
ているため、Si基板2と化合物半導体層3,3との熱膨脹
係数が異なっていてもこれら相互の伸縮が相殺されてこ
の半導体ウエハ1がそったり或はクラックが発生したり
することがない。尚、化合物半導体層3,3は複数層でも
よいが、同時に成長される同志は必ず同厚、同材質でな
ければならない。FIG. 1 is an explanatory view showing a semiconductor wafer in which compound semiconductor layers are formed on both main surfaces of a Si substrate, and the compound semiconductor layers 3 of the same thickness and the same material are formed on the two mirror-finished main surfaces of the Si substrate 2. 3 For example, an epitaxial growth layer of GaAs, GaAsP, GaAlAs or the like is formed. Since the compound semiconductor layers 3 and 3 are simultaneously grown on both main surfaces of the Si substrate 2 by the manufacturing method described below, even if the Si substrate 2 and the compound semiconductor layers 3 and 3 have different thermal expansion coefficients. These mutual expansions and contractions do not cancel each other, so that the semiconductor wafer 1 does not warp or cracks occur. Note that the compound semiconductor layers 3 and 3 may be a plurality of layers, but the same layers grown at the same time must always have the same thickness and the same material.
次に、従来の半導体ウエハの製造方法を図示した第2図
により説明する。Next, a conventional method for manufacturing a semiconductor wafer will be described with reference to FIG.
第2図は従来の半導体ウエハの製造方法を実施するため
の横型気相成長を示す説明図である。FIG. 2 is an explanatory view showing horizontal vapor deposition for carrying out a conventional semiconductor wafer manufacturing method.
Si基板2はその一端がウエハ支持具4に固定されて反応
管5内にセットされている。このSi基板2の両主面を赤
外線ランプ6,6で均一に加熱し、反応管5のガス導入口5
aから成長させる化合物半導体の原料ガスを供給する
と、原料ガスはSi基板2の両主面上(図面においては上
側及び下側)を同量流れ、これにより同じ厚さの化合物
半導体エピタキシャル成長層3,3がSi基板2上に形成さ
れる。尚、排気ガスは排気口5bから排出される。又、図
中矢印はガスの流れを示している。このようにして得ら
れた半導体ウエハ1は、Si基板2の両主面に同厚、同材
質の化合物半導体エピタキシャル層3が同時に成長され
ているため、そり及びクラックが発生することがない。One end of the Si substrate 2 is fixed to the wafer support 4 and set in the reaction tube 5. Both main surfaces of the Si substrate 2 are uniformly heated by the infrared lamps 6 and 6 and the gas introduction port 5 of the reaction tube 5 is heated.
When the source gas of the compound semiconductor to be grown from a is supplied, the source gas flows in the same amount on both main surfaces of the Si substrate 2 (upper side and lower side in the drawing), whereby the compound semiconductor epitaxial growth layer 3 having the same thickness, 3 is formed on the Si substrate 2. The exhaust gas is discharged from the exhaust port 5b. The arrows in the figure indicate the flow of gas. Since the semiconductor wafer 1 thus obtained has the compound semiconductor epitaxial layers 3 of the same thickness and the same material grown on both main surfaces of the Si substrate 2 at the same time, warpage and cracks do not occur.
しかしながら、従来の横型気相成長装置では、一度に1
枚乃至数枚の成長が限界であった。However, in the conventional horizontal vapor phase epitaxy apparatus, one at a time
The growth was limited to one or several sheets.
[発明の目的] 本発明の目的は、前記した従来技術の問題点を解消し、
Si基板に化合物半導体をエピタキシャル成長させてもク
ラック及びそりが発生することのない半導体ウエハを量
産できる製造方法を提供することにある。[Object of the Invention] An object of the present invention is to solve the above-mentioned problems of the prior art,
It is an object of the present invention to provide a manufacturing method capable of mass-producing semiconductor wafers in which cracks and warpage do not occur even when a compound semiconductor is epitaxially grown on a Si substrate.
[発明の概要] 本発明の要旨は、反応管内で支持されたSi基板の両主面
を加熱しながら該両主面に上記反応管内に供給した原料
ガスを接触させて、少なくとも一層以上の同材質の化合
物半導体層を上記Si基板の両主面に同時にエピタキシャ
ル成長させる半導体ウエハの製造方法において、上部に
原料ガス導入口を有しかつ側壁下部に放射状に延びる複
数の排気口を有する反応管の内側に内管を設置して該内
管と上記反応管との間にガス流通路を形成し、該ガス流
通路内に設けた円筒状ウエハ支持具に複数枚の上記Si基
板をその一方の主面を上記内管の中心に向けてそれぞれ
支持すると共に、上記円筒状ウエハ支持具により上記反
応管の原料ガス導入口から供給した原料ガスの流れを内
側ガス流通路と外側ガス流通路に分流しかつ該外側ガス
流通路を通過した排気ガスを直接上記排気口から排出し
上記内側ガス流通路を通過した排気ガスを上記円筒状ウ
エハ支持具の底部に設けた孔を通して上記排気口から排
出し、同時に上記内管の内側に設置された内側加熱体と
上記反応管の外周を取り囲むように設置された外側加熱
体により上記複数枚のSi基板の両主面を加熱することを
特徴とする半導体ウエハの製造方法にある。[Summary of the Invention] The gist of the present invention is to heat at least both main surfaces of a Si substrate supported in a reaction tube while bringing the source gas supplied into the reaction tube into contact with the both main surfaces, and at least one layer In a method of manufacturing a semiconductor wafer in which a compound semiconductor layer of a material is epitaxially grown on both main surfaces of the Si substrate at the same time, inside a reaction tube having a raw material gas inlet at an upper portion and a plurality of exhaust outlets radially extending at a lower portion of a sidewall An inner tube is installed in the chamber to form a gas flow path between the inner tube and the reaction tube, and a plurality of the Si substrates are mounted on a cylindrical wafer support provided in the gas flow path. The surface is supported toward the center of the inner tube, and the flow of the raw material gas supplied from the raw material gas introduction port of the reaction tube is divided into the inner gas flow passage and the outer gas flow passage by the cylindrical wafer support. And the outside gas distribution The exhaust gas that has passed through the passage is directly discharged from the exhaust port, and the exhaust gas that has passed through the inner gas flow passage is discharged from the exhaust port through a hole provided at the bottom of the cylindrical wafer support, and at the same time, the inner pipe A method of manufacturing a semiconductor wafer, comprising heating both main surfaces of the plurality of Si substrates by an inner heating element installed inside and an outer heating element installed so as to surround the outer periphery of the reaction tube. .
[実施例] 以下、本発明の実施例を図面に基づいて説明する。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
第3図は本発明の半導体ウエハの製造方法を実施するた
めの縦型気相成長装置を示す説明図であり、第3図
(a)は正面から見た図、第3図(b)は第3図(a)
におけるA−A断面図、第3図(c)は第3図(a)に
おけるB−B断面図である。FIG. 3 is an explanatory view showing a vertical type vapor phase growth apparatus for carrying out the method for manufacturing a semiconductor wafer of the present invention. FIG. 3 (a) is a front view and FIG. 3 (b) is Fig. 3 (a)
3 is a cross-sectional view taken along line AA in FIG. 3, and FIG. 3C is a cross-sectional view taken along line BB in FIG.
図において12はガス導入口12a及び排気口12cを有する石
英製の反応管、13は反応管12内に設置されガス流通路12
bを形成するための内管、14はSi基板2の一端を支持す
るためのウエハ支持具、15及び16はSi基板2の両主面を
均一に加熱するための赤外線ランプである。この縦型気
相成長装置は、複数枚のSi基板2の両主面に同時に化合
物半導体層3,3を成長させることができるため、第2図
で説明した従来の横型気相成長装置に比較して量産性に
優れている。In the figure, 12 is a quartz reaction tube having a gas inlet 12a and an outlet 12c, and 13 is a gas flow passage 12 installed in the reaction tube 12.
An inner tube for forming b, 14 is a wafer support for supporting one end of the Si substrate 2, and 15 and 16 are infrared lamps for uniformly heating both main surfaces of the Si substrate 2. This vertical vapor phase growth apparatus can grow compound semiconductor layers 3, 3 on both main surfaces of a plurality of Si substrates 2 at the same time, so that it can be compared with the conventional horizontal vapor phase growth apparatus described in FIG. And has excellent mass productivity.
ガス導入口12aから導入された成長される化合物半導体
の原料ガスは、ガス流通路12bを通り、赤外線ランプ15,
16により均一に加熱されたSi基板2の両主面上を流れ、
反応して生成した化合物半導体は、Si基板2の両主面上
に同じ厚さ成長する。尚、反応後のガスは、内管13、ウ
エハ支持具14、反応管12の夫々の隙間を流れて排出口12
cから排出されるが、内管13とウエハ支持具14の間を流
れるガスはウエハ支持具14の底部に設けた孔14aから排
出口12cへ排出されるようにしてある。又、図中矢印は
ガスの流れを示している。このようにして得られた半導
体ウエハ1は前記横型気相成長装置で得られたものと同
様にそり及びクラックが発生することがない。The raw material gas of the compound semiconductor to be grown introduced from the gas inlet 12a passes through the gas flow passage 12b, the infrared lamp 15,
Flowing on both main surfaces of the Si substrate 2 heated uniformly by 16
The compound semiconductor produced by the reaction grows to the same thickness on both main surfaces of the Si substrate 2. The gas after the reaction flows through the gaps between the inner tube 13, the wafer support tool 14, and the reaction tube 12, and is discharged through the discharge port 12
Although the gas is discharged from c, the gas flowing between the inner tube 13 and the wafer support 14 is discharged from the hole 14a provided at the bottom of the wafer support 14 to the discharge port 12c. The arrows in the figure indicate the flow of gas. The semiconductor wafer 1 thus obtained is free from warpage and cracks as in the case of using the horizontal vapor phase growth apparatus.
実施例1 厚さが300μm、主面が(100)面から2°OFFしたSi基
板(両主面は鏡面)を8枚使用し、原料ガスとしてGa(C
H3)3、Al(CH3)3、AsH3、n型ドーパントガスとしてSi
H4、キャリアガスとしてH2を使用し、第2図に示す装置
により各Si基板の両主面にn型GaAlAsを各々20μm成長
させた。この得られた8枚の半導体ウエハにはそり及び
クラックが全く発生しておらず、電気的特性も良好であ
った。Example 1 Eight Si substrates each having a thickness of 300 μm and whose main surface was 2 ° off from the (100) surface (both main surfaces were mirror surfaces) were used, and Ga (C
H 3) 3, Al (CH 3) 3, Si as AsH 3, n-type dopant gas
Using H 4 and H 2 as a carrier gas, n-type GaAlAs was grown to 20 μm on both main surfaces of each Si substrate by the apparatus shown in FIG. The obtained eight semiconductor wafers had no warpage and cracks and had good electrical characteristics.
実施例2 上記実施例1と同様な方法により厚さ300μm、Si基板
8枚の両主面にGaAlAsを20μm成長させた後、H2ガス以
外の供給を停止して放置し、その後、原料ガスとしてGa
(CH3)3、AsH3、P型ドーパントガスとしてZn(CH2CH3)2
を供給し、p型GaAs層を各々5μm成長させた。この場
合も得られた8枚の半導体ウエハにそり及びクラックは
発生せず、電気的特性も良好であった。Example 2 After growing GaAlAs to 20 μm on both main surfaces of eight Si substrates having a thickness of 300 μm by the same method as in Example 1 described above, supply of gases other than H 2 gas was stopped, and the raw material gas was left. As Ga
(CH 3 ) 3 , AsH 3 , Zn (CH 2 CH 3 ) 2 as P-type dopant gas
Was supplied to grow a p-type GaAs layer to a thickness of 5 μm. Also in this case, warpage and cracks did not occur in the obtained eight semiconductor wafers, and the electrical characteristics were good.
[発明の効果] 以上に説明した如く、本発明の半導体ウエハの製造方法
によれば次ような顕著な効果を奏する。[Effects of the Invention] As described above, the method for manufacturing a semiconductor wafer of the present invention has the following remarkable effects.
(1)Si基板の鏡面加工された両主面に、エピタキシャ
ル成長により同時に同厚かつ同材質の化合物半導体層を
少なくとも一層以上形成できるため、この半導体ウエハ
にそり及びクラックが発生することがない。(1) Since at least one compound semiconductor layer having the same thickness and the same material can be simultaneously formed on both mirror-finished main surfaces of the Si substrate by epitaxial growth, warpage and cracks do not occur in this semiconductor wafer.
(2)上記したそり及びクラックが発生していない半導
体ウエハを、1回のエピタキシャル成長で複数枚同時に
製造でき、量産性に優れている。(2) A plurality of semiconductor wafers free from the above-mentioned warpage and cracks can be simultaneously manufactured by one epitaxial growth, and the mass productivity is excellent.
第1図は半導体ウエハを示す説明図、第2図は従来例を
示す説明図、第3図は本発明の半導体ウエハの製造方法
の一実施例を示す説明図である。 1:半導体ウエハ、2:Si基板、3:化合物半導体層。FIG. 1 is an explanatory diagram showing a semiconductor wafer, FIG. 2 is an explanatory diagram showing a conventional example, and FIG. 3 is an explanatory diagram showing one embodiment of a semiconductor wafer manufacturing method of the present invention. 1: semiconductor wafer, 2: Si substrate, 3: compound semiconductor layer.
Claims (1)
熱しながら該両主面に上記反応管内に供給した原料ガス
を接触させて、少なくとも一層以上の同材質の化合物半
導体層を上記Si基板の両主面に同時にエピタキシャル成
長させる半導体ウエハの製造方法において、上部に原料
ガス導入口を有しかつ側壁下部に放射状に延びる複数の
排気口を有する反応管の内側に内管を設置して該内管と
上記反応管との間にガス流通路を形成し、該ガス流通路
内に設けた円筒状ウエハ支持具に複数枚の上記Si基板を
その一方の主面を上記内管の中心に向けてそれぞれ支持
すると共に、上記円筒状ウエハ支持具により上記反応管
の原料ガス導入口から供給した原料ガスの流れを内側ガ
ス流通路と外側ガス流通路に分流しかつ該外側ガス流通
路を通過した排気ガスを直接上記排気口から排出し上記
内側ガス流通路を通過した排気ガスを上記円筒状ウエハ
支持具の底部に設けた孔を通して上記排気口から排出
し、同時に上記内管の内側に設置された内側加熱体と上
記反応管の外周を取り囲むように設置された外側加熱体
により上記複数枚のSi基板の両主面を加熱することを特
徴とする半導体ウエハの製造方法。1. A heating method for heating both main surfaces of a Si substrate supported in a reaction tube to bring the source gas supplied into the reaction tube into contact with the both main surfaces to form at least one or more compound semiconductor layers of the same material. In the method for manufacturing a semiconductor wafer in which both main surfaces of the Si substrate are epitaxially grown at the same time, an inner tube is provided inside a reaction tube having a source gas introduction port in the upper part and a plurality of exhaust ports extending radially in the lower part of the side wall. A gas flow passage is formed between the inner pipe and the reaction pipe, and a plurality of the Si substrates are provided on a cylindrical wafer support provided in the gas flow passage, one main surface of which is the inner pipe of the inner pipe. While supporting toward the center respectively, the flow of the raw material gas supplied from the raw material gas introduction port of the reaction tube by the cylindrical wafer support is divided into an inner gas flow passage and an outer gas flow passage, and the outer gas flow passage is provided. Exhaust gas that passed Exhausted directly from the exhaust port and passing through the inner gas flow passage, exhaust gas is exhausted from the exhaust port through a hole provided at the bottom of the cylindrical wafer support, and at the same time, the inner side installed inside the inner pipe. A method of manufacturing a semiconductor wafer, comprising heating both main surfaces of the plurality of Si substrates with a heating body and an outer heating body provided so as to surround the outer circumference of the reaction tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139365A JPH0760803B2 (en) | 1987-06-03 | 1987-06-03 | Method for manufacturing semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139365A JPH0760803B2 (en) | 1987-06-03 | 1987-06-03 | Method for manufacturing semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63304618A JPS63304618A (en) | 1988-12-12 |
| JPH0760803B2 true JPH0760803B2 (en) | 1995-06-28 |
Family
ID=15243632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62139365A Expired - Fee Related JPH0760803B2 (en) | 1987-06-03 | 1987-06-03 | Method for manufacturing semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760803B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4964430B2 (en) * | 2005-05-25 | 2012-06-27 | 昭和電工株式会社 | Semiconductor element forming substrate, epitaxial wafer, and semiconductor element and semiconductor device using them |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62101024A (en) * | 1985-10-28 | 1987-05-11 | Sumitomo Electric Ind Ltd | Epitaxial-growth wafer |
-
1987
- 1987-06-03 JP JP62139365A patent/JPH0760803B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63304618A (en) | 1988-12-12 |
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