JPH0760867B2 - Non-volatile semiconductor memory - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same, and more particularly, to an ultraviolet erasable rewritable read-only memory (hereinafter referred to as EPROM). Abbreviated as “) and a method of forming the same.

(Prior Art) Conventionally, for example, a memory cell transistor in an EPROM using a P-type silicon substrate has a structure as shown in FIG. That is, a gate electrode having a two-layer structure in which the gate oxide film 52, the floating gate electrode 53, the first insulating film 54, the control gate electrode 55, and the second insulating film 56 are sequentially stacked on the element region of the semiconductor substrate 51. Part is formed, and on both sides of the channel region of the semiconductor substrate below the gate electrode part, impurity diffusion layer regions 57 to be the source region / drain region of the MOS transistor,
58 is formed, and at the same time when the second insulating film 56 is formed, the same insulating film 56 is formed on the side surface of the gate electrode portion, and an interlayer insulating film 60 is formed on the impurity diffusion layer region and the gate electrode portion. One of the impurity diffusion layer regions (for example, the drain region 5) is formed through the contact hole formed in the insulating film 60.
Metal wiring (for example, aluminum wiring 61) is formed so as to contact 8).

However, since the contact hole is formed by using a field oxide film (not shown) for element isolation as a reference for mask alignment, it is necessary to sufficiently consider the margin for mask misalignment. Without it, in the extreme case, the second insulating film on the side surface of the gate electrode part
Since 56 is etched, the insulating property between the aluminum wiring 61 and the gate electrodes 55 and 53 of the memory cell transistor becomes a problem.

Therefore, the above-mentioned conventional EPROM requires a certain fixed amount determined by the exposure system or the like as a margin of alignment between the gate electrode and the contact hole for the metal wiring when the cell is miniaturized. There was a problem that the interval could not be shortened.

In view of the above-mentioned circumstances, the present inventor has made it possible to reduce the alignment margin between the gate electrode and the contact hole at the time of opening the contact for metal wiring, and to miniaturize the cell, and the manufacturing thereof. A method has already been proposed (Japanese Patent Application No. 63-78980 relating to the applicant's application).
issue). An example of the semiconductor integrated circuit according to the above application is shown in FIGS. 6 (a) to 6 (d), FIG. 6 (a) shows a pattern plane, and FIGS. 6 (b), (c), ( d) correspond to XX line, YY line, Y'of FIG. 6 (a), respectively.
The cross-sectional structure taken along the line -Y 'is shown.

This semiconductor integrated circuit has an array of memory cells composed of floating gate type MOS transistors in which a source region 78 and a drain region 79 are formed in a self-aligned manner with respect to a laminated structure pattern of a floating gate electrode 74 and a control gate electrode 76. An insulating film 77 is formed on the upper surface and the side surface of the gate electrode portion, and the channel-side end portion of the drain region 79 serves as an impurity region having a lower concentration than the remaining portion by using the insulating film 77 on the side surface as an offset region. A conductive film 80 made of a low resistance material is formed so as to cover the surface of the drain region 79 and the insulating film 77 on at least the side surface of the gate electrode portion on both ends of the drain region 79, and on the conductive film 80. The metal wiring 82 is deposited in a self-aligned manner to form a contact portion. Reference numeral 71 is a semiconductor substrate, 72 is a field oxide film for element isolation, 73 is a gate oxide film, 75 is an insulating film, and 81 is an interlayer insulating film.

According to the semiconductor integrated circuit of FIG. 6, the contact margin between the gate electrode and the contact hole can be reduced when the contact hole for metal wiring is opened, and the cell can be miniaturized.

However, in order to make contact between the conductive film 80 and the metal wiring 82, when the interlayer insulating film 81 formed on the conductive film 80 and the substrate 71 is etched to form a contact hole, the contact holes are misaligned. Must be sufficiently considered. If this alignment margin is not available, the insulating film 77 on the side surface of the gate electrode portion is etched, and the insulation between the metal wiring 82 and the gate electrodes 76 and 74 of the memory cell transistor is reduced. Becomes a problem, and thus becomes a problem when the cell is further miniaturized.

In addition, the EPROM erases data by irradiating ultraviolet rays from the outside to extract the electric charge accumulated in the floating gate electrode 74. Therefore, in the semiconductor integrated circuit shown in FIG. 6, when the area covered by the conductive film 80 (the shaded area in FIG. 6a) increases, the amount of ultraviolet rays blocked by the conductive film 80 increases, and Since it is possible to prevent intrusion, it becomes difficult to erase the data in the EPROM cell.
Moreover, when the periphery of the EPROM cell is widely covered with the conductive film 80, the efficiency of discharging charges from the floating gate electrode 74 to the semiconductor substrate 71 is remarkably reduced, and the data erasing efficiency of the EPROM cell is remarkably reduced. I will end up.

(Problems to be Solved by the Invention) The present invention is based on the EPROM of the semiconductor integrated circuit of FIG.
When opening a contact for metal wiring of a cell, a margin for mask alignment between a conductive film of a low resistance material and a contact hole is required, which causes a problem in further miniaturizing the cell. This was done in view of the problem that the increase in the area covered by the conductive film of the EPROM significantly reduces the efficiency of erasing the data in the EPROM cell due to UV irradiation. When forming holes, the alignment margin between the gate electrode and the contact hole can be reduced, and there are few places to secure the alignment margin between the conductive film made of a low resistance material and the contact hole for the metal wiring, and the cell is further miniaturized. It is an object of the present invention to provide a non-volatile semiconductor memory that is capable of improving the efficiency of erasing cell data due to ultraviolet irradiation.

[Configuration of the Invention] (Means for Solving the Problems) A nonvolatile semiconductor memory according to the present invention includes a floating gate electrode formed on a semiconductor substrate via a gate insulating film, and a first floating gate electrode on the floating gate electrode. A control gate electrode formed through an insulating film and a second gate formed on the control gate electrode
A non-volatile memory cell array having a source region and a drain region formed in the semiconductor substrate in a self-aligned manner with respect to a gate portion in which the floating gate electrode and the control gate electrode are stacked. In the nonvolatile semiconductor memory having, a third insulating film formed on a side surface of the gate portion, a part of an upper surface of the gate portion and a predetermined region including the third insulating film are formed to be covered. The fourth insulating film was formed continuously for a plurality of memory cells so as to cover a part of the fourth insulating film and to contact a part of the source region or the drain region. A conductive film of a low resistance material, an interlayer insulating film formed on a semiconductor substrate including the conductive film, and an interlayer insulating film formed on the interlayer insulating film for a plurality of memory cells. Characterized in that through the contact hole formed at the rate of one point; and a formed metal wire so as to contact to the conductive film.

(Operation) According to the above-mentioned nonvolatile semiconductor memory, since the conductive film of the low resistance material is formed so as to contact a part of the drain region of the EPROM cell, when the contact opening for the metal wiring is formed, the gate electrode It is possible to reduce the alignment margin between the contact hole and the contact hole. Further, since the metal wiring is formed so as to contact the conductive film of the low resistance material through the contact holes formed at a ratio of one to a plurality of memory cells, the conductive film of the low resistance material and the metal wiring are formed. There are few places to leave a margin for mask alignment with the contact hole. Therefore, the memory cell can be further miniaturized. In addition, since the conductive film made of a low-resistance material and the metal wiring are not contacted with each other in a normal memory cell portion, it is necessary to allow for a mask alignment between the conductive film made of the low-resistance material and the contact hole for the metal wiring. The width of the conductive film made of the low resistance material can be made narrower, the irradiation amount of ultraviolet rays is increased, and the data erasing characteristic of the EPROM cell is improved.

(Embodiment) Hereinafter, an embodiment of a nonvolatile semiconductor memory and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.

FIGS. 1 (a) to 1 (e) show plane patterns in the EPROM manufacturing process, and are taken along line XX in FIG. 1 (e).
The cross-sectional structure in each step along the YY line and the Y′-Y ′ line is
2 (a) to 2 (j), 3 (a) to 3 (h), and 3 (a) to 3 (g), respectively.

First, as shown in FIGS. 2A, 3A, and 4A, a field oxide film 2 is formed on the surface of a semiconductor substrate (for example, a P-type silicon substrate) 1 by a known technique. It is formed and element isolation is performed. Next, on the surface of the substrate 1, a thickness of 200Å
The gate oxide film 3 having a certain degree is formed by a thermal oxidation method. Then, a film having a thickness of 40 is formed on the entire surface of the substrate 1 by, for example, a vapor phase epitaxy method.
After forming the first polycrystalline silicon film 4 having a thickness of about 00Å, impurities such as phosphorus are ion-implanted into the polycrystalline silicon film 4, or doped by a thermal diffusion method using POCl ₃ as a diffusion source. Next, after removing the slit portion of the polycrystalline silicon film 4 using a resist mask, a thickness of about 350Å is formed on the polycrystalline silicon film 4 as a first insulating film by, for example, a diluting oxidation method at 900 ° C to 1000 ° C. Then, the silicon oxide film 5 is formed. Next, after depositing the second polycrystalline silicon film 6 on the entire surface of the substrate 1 by, for example, a vapor phase growth method, impurities such as phosphorus are ion-implanted into the polycrystalline silicon film 6. Further, a silicate glass containing, for example, phosphorus, for example, a phosphorus silicate glass (PSG film) 7 is deposited as a second insulating film on the entire surface of the substrate 1, and a resist pattern 8 is formed thereon.

Next, as shown in FIG. 2 (b), FIG. 3 (b), and FIG. 4 (b), the PSG film 7, the second polycrystalline silicon film 6, and the silicon oxide are used with the resist pattern 8 as a mask. The film 5, the first polycrystalline silicon film 4 and the gate oxide film 3 are sequentially and selectively etched by anisotropic etching to form a gate electrode portion of a memory cell transistor. Next, after removing the resist pattern 8, in order to form a low-concentration n ⁻ diffusion region in the drain region, for example, arsenic ions are implanted into the substrate 1 at an acceleration voltage of 120 KeV to about 1 × 10 ¹³ cm ⁻² , and then, , Acceleration voltage of arsenic ions on the surface of substrate 1 40
Inject about 1 to 7 × 10 ¹⁴ cm ^{-2 with} KeV. Subsequently, the drain region is covered with a resist 9 and, for example, arsenic ions are implanted into the source region at an acceleration voltage of 40 KeV at about 2 × 10 ¹⁵ cm ^-2 .

Next, after removing the resist 9, as shown in FIG. 2C, a third insulating film is formed on the side surface of the gate electrode portion.
For example, the thermal oxide film 10 having a thickness of about 350 Å is formed by the thermal oxidation method. At the same time, the thickness of 200
A thermal oxide film 10 of about Å is formed. Also, in this process,
As described above, the ion-implanted arsenic diffuses to form a high-concentration n ⁺ diffusion region 11 on the source side and two low-concentration n ⁻ diffusion regions 12 on the drain side.

Then, for example, phosphorus ions are applied to the entire surface of the substrate 1 by accelerating voltage.
Implanted at about 5 × 10 ¹⁴ cm ^-2 at 20 KeV to convert the thermal oxide film 10 into PSG, and subsequently, as shown in FIG. 2 (d), FIG. 3 (c) and FIG. 4 (c), the substrate For example, PSG film 13 on the entire surface
Deposit.

Subsequently, as shown in FIG. 2E, a resist 14 having a contact hole pattern of such a size as to cover the gate electrode portion is formed on the PSG film 13.

Then, as shown in FIGS. 2 (f) and 3 (d), reactive ion etching (RI) is performed using the resist 14 as a mask.
E) method is used to etch the PSG film 13 and the thermal oxide film 10 on the substrate 1 to form a fourth surface on the drain side surface of the gate electrode portion.
A PSG side wall portion 13 is formed as an insulating film of and the bottom portion of the contact hole on the drain region is exposed.

Next, a third polycrystalline silicon film is deposited on the entire surface of the substrate 1 by, for example, a vapor phase growth method. Then, in order to form a high-concentration n ⁺ diffusion region in the drain region, for example, arsenic ions are implanted into the entire surface of the substrate 1 at an acceleration voltage of 150 KeV at about 5 × 10 ¹⁵ cm ^-2 . Further, for example, a titanium Ti film is deposited on the entire surface of the substrate 1 by a sputtering method, and sintering is performed to form a silicide between the titanium Ti film and the third polycrystalline silicon film.
As shown in FIG. 3G, a titanium silicide TiSi ₂ film 16 is formed. At this time, simultaneously, a high-concentration n ⁺ diffusion region 17 is formed on the drain side, and an LDD (Lightly Doped Drain) structure is obtained.

Next, with reference to the field oxide film 2, FIG.
The resist 18 is patterned and the TiSi
₂ film 16 is etched to form TiSi ₂ film wiring 16 continuously for a plurality of memory cell transistors in a predetermined direction shown in FIGS. 3 (e) and 4 (d).

Next, as shown in FIG. 2 (h), FIG. 3 (f), and FIG. 4 (e), for example, low pressure vapor deposition (LPCVD) is performed on the entire surface of the substrate 1 as an interlayer insulating film (passivation film). ) Method is used to form a CVD oxide film 19.

Then, as shown in FIGS. 2 (i), 3 (g) and 4 (f), a contact for contacting the TiSi ₂ film wiring 16 and the metal wiring (for example, aluminum wiring 21). In order to open the hole, the CVD oxide film 19 is etched using the TiSi ₂ film wiring 16 as a stopper. In this case, the resist pattern 20 for opening the contact holes is formed as shown in FIG. 1 (d) so that one contact hole is opened above the source region for a plurality of memory cell transistors.
It is formed as shown in.

Next, as shown in FIG. 2 (j), for example, an aluminum film 21 is deposited on the entire surface of the substrate 1 (including the inside of the contact hole) by a sputtering method, and then the aluminum film 21 is deposited on the aluminum film 21 as shown in FIG. The resist 22 is applied as shown in FIG. 3A), and the resist 22 is patterned with reference to the resist pattern 20 of the contact hole opening. Then, as shown in FIGS. 3H and 4G, the aluminum film 21 is patterned by using the resist 22 as a mask to form the aluminum wiring 21.

Thereafter, although not shown, a protective insulating film and a pad on the aluminum wiring 21 are formed in accordance with a usual MOS semiconductor integrated circuit manufacturing process to realize a desired EPROM integrated circuit.

Although the formation of the contact portion for the drain region has been described in the above embodiment, the contact portion for the source region is also formed by the same self-aligned contact forming method as described above.

In the EPROM manufactured as described above, a conductive film made of a low resistance material such as the TiSi ₂ film 16 (hereinafter, referred to as a low resistance material) so as to contact a part of the source region or the drain region of the EPROM cell. Since the conductive film) is formed, it is possible to reduce the alignment margin between the gate electrodes 6 and 4 and the contact hole when the contact hole for the aluminum wiring 21 is opened. Further, since the aluminum wiring 21 is formed so as to contact the conductive film 16 of low resistance material through the contact hole formed at one place for a plurality of memory cells, the conductive film 16 of low resistance material is formed.
It is possible to reduce the number of places to allow a mask to be aligned with the contact hole for aluminum wiring 21.

That is, in the above EPROM, due to the difference in the way of making contact between the diffusion layer region and the bit line, A in FIG.
It has two types of structures, such as a part and a part B. In the portion A, the diffusion layer region 17 for the drain is in contact with the low resistance material conductive film 16, but is not in contact with the aluminum wiring 21.
Is in contact with the conductive film 16 made of a low resistance material above the diffusion layer region 11 for the source as shown in part B.

Therefore, in the portion A (normal memory cell portion), the drain contact region is formed in a self-aligned manner in the XX line direction, and the gate electrodes 6 and 4 and the aluminum wiring 21 are formed.
It is not necessary to have a margin to align with the contact hole for use. Further, since the conductive film 16 of the low resistance material and the aluminum wiring 21 are not contacted with each other in the portion A, a margin for mask alignment between the conductive film 16 of the low resistance material and the contact hole for the aluminum wiring 21 is expected. It is not necessary to make the width (Y-Y direction) of the conductive film 16 of low resistance material narrow, the ratio of blocking ultraviolet rays is reduced, the ultraviolet irradiation amount is increased, and the data erasing efficiency of the EPROM cell is increased. And the erasing time is shortened and the erasing characteristics are improved.

Since the conductive film 16 of the low resistance material is continuously connected when viewed in the XX line direction, the area of the conductive film 16 of the low resistance material is increased by the conventional EPROM. Since the conductive film 16 of the resistance material is formed under the aluminum wiring 21, it does not adversely affect the erasing efficiency.

On the other hand, in this embodiment, the B type is formed on the diffusion layer region 11 on the source side of the memory cell transistor, and the aluminum wiring 21 is in contact with the conductive film 16 of the low resistance material. The conductive film 16 of the low resistance material is formed in consideration of a margin for mask alignment with the contact hole for the aluminum wiring 21. Therefore, the distance between the contact hole portion and the gate electrode portion of the transistor is formed to be slightly longer so as not to reduce the erase efficiency of the memory cell transistor adjacent to the contact hole portion for the aluminum wiring 21. Further, since the conductive film 16 of low resistance material is used, the contact between the aluminum wiring 21 and the conductive film 16 of low resistance material is, for example, TiSi ₂
Considering the conductivity of, for example, it is enough to provide one location for 100 transistors.

Therefore, according to the above EPROM, when viewed as a whole, EPR
It is possible to reduce the alignment margin between the gate electrode of the OM cell and the contact hole for aluminum wiring, which enables further miniaturization and higher integration of the cell, and moreover, cell data erasing efficiency by ultraviolet irradiation. Is improved.

Further, in the above embodiment, since the EPROM cell has the LDD structure, the peak electrolytic strength in the region near the drain during the read operation is relaxed, and errors such as soft write due to the generation of hot electrons can be prevented.

In the above embodiment, the contact between the conductive film 16 of low resistance material and the aluminum wiring 21 is taken above the diffusion layer region for the source, but when the contact is taken above the diffusion layer region for the drain. However, the same effect as the above embodiment can be obtained. In this case, as in the above embodiment, aluminum wiring
21 and a method of making contact between the low resistance material conductive film 16 and the aluminum wiring 21 and the low resistance material conductive film 16
Conductive film of low resistance material where contact is formed
There is a method of making a contact between 16 and the diffusion layer region 17.

Further, in the above embodiment, the contact between the aluminum wiring 21 and the conductive film 16 of the low resistance material is made in the memory cell array. However, one contact is provided outside the memory cell array for a plurality of memory cell transistors. Even when the contacts are collectively made at the ratio of, the same effect as that of the above-described embodiment can be obtained.

According to the EPROM manufacturing method as described above, an EPROM having the above-described features can be easily formed.

The conductive film 16 made of a low-resistance material is made of Ti in the above-mentioned embodiment.
Various materials such as silicide (WSi ₂ etc.) other than Si ₂ , refractory metal such as tungsten or molybdenum, or polysilicon doped with impurities can be used. You can change part of the process.

As described above, according to the present invention, the alignment margin between the gate electrode of the EPROM cell and the contact hole for the metal wiring and the mask alignment between the conductive film of the low resistance material and the contact hole for the metal wiring can be achieved. Since the margins can be reduced, the cells can be miniaturized, and a nonvolatile semiconductor memory in which the efficiency of erasing cell data by irradiation of ultraviolet rays is improved can be realized.

[Brief description of drawings]

1 (a) to 1 (e) are EPROs according to an embodiment of the present invention.
FIG. 2 (a) to FIG. 2 (j) is a plan view of a memory cell for explaining the manufacturing method of M, and FIG.
-Figure showing a manufacturing process in a cross section along the X-ray, FIG.
1 to (h) are views showing a manufacturing process in a section taken along the line YY of FIG. 1 (e), and FIGS. 4 (a) to (g) are Y'-Y 'of FIG. 1 (e). The figure which shows the manufacturing process in the cross section which follows the line, Figure 5 the cross section which shows the memory cell of the conventional EPROM,
FIGS. 6 (a) to 6 (d) are shown to explain one example of the currently proposed EPROM. (A) is a plan view of a memory cell, (b) is XX of (a). Sectional drawing which follows the line, (c) is sectional drawing which follows the YY line of (a), (d).
FIG. 7A is a sectional view taken along line Y′-Y ′ of FIG. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Gate insulating film, 4 ... Floating gate electrode, 5 ... First insulating film, 6 ... Control gate electrode, 7 ... Second insulating film Membrane, 8,
9, 14, 18, 20, 22 ... Resist, 10 ... Third insulating film, 11 ... Source region, 12, 17 ... Drain region, 13 ...
… 4th insulating film, 16 …… Low resistance material conductive layer, 19 …… Interlayer insulating film, 21 …… Aluminum wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (3)

[Claims] 1. A floating gate electrode formed on a semiconductor substrate via a gate insulating film, and a first floating gate electrode on the floating gate electrode.
A control gate electrode formed via the insulating film of the second insulating film, a second insulating film formed on the control gate electrode, and a gate portion in which the floating gate electrode and the control gate electrode are stacked. A non-volatile semiconductor memory having an array of non-volatile memory cells having a source region and a drain region formed on the semiconductor substrate in a consistent manner, a third insulating film formed on a side surface of the gate portion, and the gate A fourth insulating film formed so as to cover a part of an upper surface of the portion and a predetermined region including the third insulating film, and a part of the fourth insulating film and a part of the drain region. Conductive film formed of a low resistance material and continuously formed on a plurality of memory cells in a predetermined direction so as to contact the portion, and an interlayer insulating film formed on the semiconductor substrate including the conductive film. And contacting the conductive film through a contact hole formed above the interlayer insulating film and located above the source region formed in the interlayer insulating film at a ratio of one place for a plurality of memory cells. And a metal wiring formed as described above. 2. The non-volatile semiconductor memory according to claim 1, wherein the conductive film is silicide, refractory metal, or polycrystalline silicon doped with impurities. 3. The non-volatile semiconductor memory according to claim 1, wherein the conductive film is formed below the metal wiring.