JPH0760928B2 - Wiring formation method - Google Patents
Wiring formation methodInfo
- Publication number
- JPH0760928B2 JPH0760928B2 JP19165287A JP19165287A JPH0760928B2 JP H0760928 B2 JPH0760928 B2 JP H0760928B2 JP 19165287 A JP19165287 A JP 19165287A JP 19165287 A JP19165287 A JP 19165287A JP H0760928 B2 JPH0760928 B2 JP H0760928B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- metal thin
- film
- wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、各種電子デバイスにおける配線を形成する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method for forming wiring in various electronic devices.
（従来の技術） 従来から、各種電子デバイスにおける配線あるいは電極
を形成する方法として、基体上に形成した導体層からそ
の不要部分を除去して所望パターンを得るフォトリソグ
ラフィ技術が一般に知られている。(Prior Art) Conventionally, as a method of forming wirings or electrodes in various electronic devices, a photolithography technique for obtaining a desired pattern by removing an unnecessary portion from a conductor layer formed on a substrate is generally known.
なかでも薄膜技術による電子デバイスにおいては、前記
導体層として、真空蒸着法等により容易に得られる金属
薄膜が用いられており、この金属薄膜の材料としては、
安価なうえ低抵抗であることからAl等が広く用いられて
いる。また、エッチングの際に用いられるレジストとし
ては、g,h,i線等の紫外光を用いるフォトレジストが一
般であるが、レジストの剥離が容易でかつ使い易いとい
った点から、アルカリ現像が可能なフォトレジストの使
用が現在主流となっている。Among them, in the electronic device by the thin film technology, as the conductor layer, a metal thin film that is easily obtained by a vacuum deposition method or the like is used, and as a material of the metal thin film,
Al and the like are widely used because they are inexpensive and have low resistance. Further, as the resist used during etching, a photoresist using ultraviolet light such as g, h, and i rays is generally used, but alkali development is possible because the resist can be easily peeled off and used. The use of photoresists is currently the mainstream.
（発明が解決しようとする問題点） しかしながら、このような従来からの配線形成において
用いられる前記フォトレジストの現像液は有機アルカリ
系であることから、現像時にフォトレジスト膜とともに
金属薄膜の表面も浸蝕されてしまい、このことが配線の
不良原因になるといった難点があった。(Problems to be Solved by the Invention) However, since the photoresist developing solution used in such conventional wiring formation is an organic alkaline type, the surface of the metal thin film is corroded together with the photoresist film during development. However, there is a problem in that this causes defective wiring.
また、前記薄膜技術による電子デバイスのひとつである
たとえばI.T.O（Indium.Tin.Oxide）等からなる透明電
極を有する表示デバイスにおいては、前記透明電極上の
取出電極を前記配線形成と同様に前記金属薄膜からエッ
チングで形成することが通常とされているが、たとえば
膜中のゴミ等の影響により前記透明電極と前記金属薄膜
との接触部分が前記現像に侵された場合、I.T.Oの電解
腐蝕が生じ、これが表示欠陥の発生につながるといった
難点があった。Further, in a display device having a transparent electrode made of, for example, ITO (Indium.Tin.Oxide), which is one of the electronic devices based on the thin film technique, in the extraction electrode on the transparent electrode, the metal thin film is formed similarly to the wiring formation. Although it is usually formed by etching from, when the contact portion of the transparent electrode and the metal thin film due to the influence of dust in the film is affected by the development, electrolytic corrosion of ITO occurs, This has a drawback that it leads to the occurrence of display defects.
さらに、前記金属薄膜の材料として一般に用いられてい
るAlは表面の光反射率が高いことから、レジスト露光の
際に、レジスト膜内に混入したゴミ等によるレジスト膜
表面の突起が光を散乱させてしまい、この結果、レジス
トパターンが変形し、やはり導体配線の不良の原因とな
っていた。Furthermore, since Al, which is generally used as a material for the metal thin film, has a high surface light reflectance, projections on the resist film surface due to dust mixed in the resist film scatter light during resist exposure. As a result, the resist pattern is deformed, which also causes a defect in the conductor wiring.
本発明はこのような問題点を解決するためのもので、フ
ォトレジストの現像時に金属薄膜が現像液によって浸蝕
されることを防止し、かつ配線の不良発生率を大幅に低
減させることのできる配線の形成方法を提供することを
目的としている。The present invention is intended to solve such a problem, and it is possible to prevent the metal thin film from being corroded by a developing solution at the time of developing a photoresist and to significantly reduce the defect occurrence rate of the wiring. It is intended to provide a method for forming the.
［発明の構成］ （問題点を解決するための手段） 本発明は上記した目的を達成するために、基体上に着膜
された金属薄膜から、フォトレジストを用いたエッチン
グにより所望パターンの配線を形成する方法において、
前記基体上に金属薄膜を着膜した後、この金属薄膜上に
耐アルカリ性を有する保護膜を着膜し、この保護膜とと
もに前記金属薄膜を前記エッチングにより選択的に除去
して前記配線を形成することを特徴としている。[Structure of the Invention] (Means for Solving Problems) In order to achieve the above-mentioned object, the present invention provides a wiring of a desired pattern from a metal thin film deposited on a substrate by etching using a photoresist. In the method of forming,
After depositing a metal thin film on the substrate, a protective film having alkali resistance is deposited on the metal thin film, and the metal thin film together with the protective film is selectively removed by the etching to form the wiring. It is characterized by that.
（作用） 本発明の配線の形成方法において、基体上に金属薄膜を
着膜した後、この金属薄膜上に耐アルカリ性を有する保
護膜を着膜し、この保護膜とともに前記金属薄膜をフォ
トレジストを用いたエッチングにより選択的に除去して
配線を形成するようにしたので、前記金属薄膜がフォト
レジストの現像時に現像液によって浸蝕されることを防
止することが可能となり、配線の不良発生率を大幅に低
減させることができる。(Operation) In the method for forming a wiring of the present invention, after depositing a metal thin film on a substrate, a protective film having alkali resistance is deposited on the metal thin film, and the metal thin film and a photoresist are coated with a photoresist. Since the wiring is formed by selectively removing it by the etching used, it is possible to prevent the metal thin film from being corroded by the developing solution at the time of developing the photoresist, and it is possible to significantly reduce the occurrence rate of wiring defects. Can be reduced to
（実施例） 以下、本発明の実施例を図面に基づいて詳細に説明す
る。(Example) Hereinafter, the Example of this invention is described in detail based on drawing.
第１図は本発明の一実施例の配線の形成方法を示す断面
図である。FIG. 1 is a cross-sectional view showing a method of forming a wiring according to an embodiment of the present invention.
同図に示すように、この方法では、まず、絶縁基板１上
にたとえばAl等からなる金属薄膜２を真空蒸着法あるい
はスパッタ法等で着膜し、次いで、この金属薄膜２上に
たとえばMo等からなる耐アルカリ性を有する保護膜３を
真空蒸着法あるいはスパッタ法等で着膜する。As shown in the figure, in this method, first, a metal thin film 2 made of, for example, Al or the like is deposited on the insulating substrate 1 by a vacuum deposition method or a sputtering method, and then, for example, Mo or the like is deposited on the metal thin film 2. The protective film 3 having the alkali resistance is formed by a vacuum deposition method, a sputtering method or the like.
この後、保護膜３上にポジ型あるいあネガ型の感光レジ
ストを塗布し、乾燥させてレジスト膜４を形成し（第１
図−ａ）、所望のフォトマスクを介して露光してレジス
ト膜４にフォトマスクの開口パターンと等しい露光部を
形成し、さらに、有機アルカリ系の現像液を用いてその
レジスト膜４の露光部を除去する（第１図−ｂ）。Thereafter, a positive or negative photosensitive resist is applied on the protective film 3 and dried to form a resist film 4 (first
FIG. 3A) is exposed through a desired photomask to form an exposed portion having the same opening pattern as the photomask on the resist film 4, and the exposed portion of the resist film 4 is further exposed using an organic alkaline developing solution. Are removed (Fig. 1-b).
次いで、所定のエッチング液を用いてウェットエッチン
グを行い、保護膜３の露出部に対応する金属薄膜２を保
護膜３とともに除去して所望の配線パターンを形成する
（第１図−ｃ）。Then, wet etching is performed using a predetermined etching solution to remove the metal thin film 2 corresponding to the exposed portion of the protective film 3 together with the protective film 3 to form a desired wiring pattern (FIG. 1-c).
そして、最後に残存するレジスト膜４を除去して配線の
形成工程が完了する（第１図−ｄ）。なお、この状態で
残存している保護膜３は必要に応じて除去してもよい。Then, the remaining resist film 4 is removed to complete the wiring forming process (FIG. 1-d). The protective film 3 remaining in this state may be removed if necessary.
かくして、この実施例の配線の形成方法によれば、金属
薄膜２上にMo等からなる耐アルカリ性を有する保護膜３
を形成したので、レジスト膜の現像の際に、金属薄膜２
の表面が直接現像液に浸されることがなくなり、これに
より不良の発生率を大巾に低減させることが可能とな
る。さらに、この実施例の保護膜３の材料として用いた
Mo等の表面光反射率はAlに比べて極めて低いため、レジ
スト露光時の表面突起による散乱光の影響を極小に押さ
えることが可能となり、安定したレジストパターンを形
成することができ、よりいっそう配線の不良発生率を低
減させることができる。Thus, according to the wiring forming method of this embodiment, the alkali-resistant protective film 3 made of Mo or the like is formed on the metal thin film 2.
As a result, the metal thin film 2 is formed during the development of the resist film.
The surface of is not soaked directly in the developing solution, so that the occurrence rate of defects can be greatly reduced. Further, it was used as a material for the protective film 3 of this example.
Since the surface light reflectance of Mo etc. is much lower than that of Al, it is possible to minimize the influence of scattered light due to surface protrusions during resist exposure, and it is possible to form a stable resist pattern, and to further improve wiring. The defect occurrence rate can be reduced.
次に、本発明の他の実施例について説明する。Next, another embodiment of the present invention will be described.
第２図はアクティブマトリクス式の液晶表示素子におい
てスイッチング素子として用いられる薄膜トランジスタ
アレイの製造方法を示す図である。FIG. 2 is a diagram showing a method of manufacturing a thin film transistor array used as a switching element in an active matrix type liquid crystal display element.
同図に示すように、この薄膜トランジスタアレイの製造
方法では、まず、絶縁基板11上にたとえばCr等からなる
厚さ約2000Åのゲート電極12をフォトエッチング法等を
用いて形成し、さらにこの上にたとえば酸化シリコン等
からなる厚さ約35000Åの絶縁膜13、厚さ約3000Åのａ
−Si膜14および厚さ約500Åのａ−Si:n+膜15を順次真空
蒸着法等により着膜する。As shown in the figure, in the method of manufacturing the thin film transistor array, first, a gate electrode 12 made of, for example, Cr and having a thickness of about 2000 Å is formed on the insulating substrate 11 by using a photoetching method or the like, and further formed thereon. For example, an insulating film 13 made of silicon oxide or the like and having a thickness of about 35,000Å, a having a thickness of about 3000Å
The -Si film 14 and the a-Si: n + film 15 having a thickness of about 500Å are sequentially deposited by a vacuum evaporation method or the like.
この後、ａ−Si膜14およびａ−Si:n+膜15の所望パター
ンをフォトエッチング法により形成する（第２図−
ａ）。After that, desired patterns of the a-Si film 14 and the a-Si: n + film 15 are formed by photoetching (see FIG. 2-
a).
次に、絶縁膜13上に、たとえばI.T.O.等からなる厚さ約
1200Åの透明電極膜16をスパッタリング等により着膜
し、その所望のパターンをフォトエッチング法により形
成する（第２図−ｂ）。Next, on the insulating film 13, a thickness of, for example, ITO is formed.
A 1200 Å transparent electrode film 16 is deposited by sputtering or the like, and a desired pattern thereof is formed by a photoetching method (FIG. 2B).
次に、基材上に、たとえばMo等からなる耐アルカリ性を
有する保護膜17と、Al等からなる電極薄膜18と、前記同
様の保護膜19とを順次真空蒸着法またはスパッタ法等に
より積層する（第２図−ｃ）。Next, on the base material, an alkali-resistant protective film 17 made of, for example, Mo, an electrode thin film 18 made of Al, and a protective film 19 similar to the above are sequentially laminated by a vacuum deposition method or a sputtering method. (Fig. 2-c).
この後、保護膜19上にポジ型あるいはネガ型の感光レジ
ストを塗布し、乾燥させてレジスト膜20を形成し（第２
図−ｄ）、所望のフォトマスクを介して露光してレジス
ト膜20にフォトマスクの開口パターンと等しい露光部を
形成し、さらに、アルカリ系の現像液を用いてそのレジ
スト膜20の露光部を除去する（第２図−ｅ）。Then, a positive or negative photosensitive resist is applied on the protective film 19 and dried to form a resist film 20 (second
FIG. 3D), exposing through a desired photomask to form an exposed portion having the same opening pattern as the photomask on the resist film 20, and further exposing the exposed portion of the resist film 20 using an alkaline developing solution. It is removed (Fig. 2-e).
そして、所定のエッチング液を用いてエッチングを行
い、保護膜19の露出部をその下層側の金属薄膜18および
保護膜17とともに除去してソース電極、ドレイン電極お
よびシグナル配線の各所望パターンを形成し、この後残
存するレジスト膜20を除去して工程完了となる（第２図
−ｆ）。Then, etching is performed using a predetermined etching solution, and the exposed portion of the protective film 19 is removed together with the metal thin film 18 and the protective film 17 on the lower layer side to form desired patterns of the source electrode, the drain electrode and the signal wiring. After that, the resist film 20 remaining is removed to complete the process (FIG. 2F).
こうして、透明電極膜16と、これに蓄積する電荷量を制
御する能動素子としての薄膜トランジスタとを電気的に
接続する配線を得ることができる。In this way, it is possible to obtain a wiring that electrically connects the transparent electrode film 16 and a thin film transistor as an active element that controls the amount of charges accumulated therein.
かくして、この実施例によれば、金属薄膜18の上下にMo
等からなる耐アルカリ性を有する保護膜17、19を形成し
たので、レジスト膜の現像の際に、金属薄膜18の表面が
直接現像液に浸されることがなくなり、不良の発生率を
低減させることが可能となるとともに、透明電極膜16と
金属薄膜18の接触部分も現像液にさらされることがなく
なるので、透明電極膜16の電解腐蝕を防止することが可
能となり、これにより表示欠陥の発生率も極めて低減さ
せることができる。さらに、この実施例の保護膜17、19
の材料として用いたMo等の表面光反射率はAlに比べて極
めて低いため、レジスト露光時の表面突起による散乱光
の影響を極小に押さえることが可能となり、よりいっそ
う配線の不良発生率を低減させることができる。Thus, according to this embodiment, Mo is formed above and below the metal thin film 18.
Since the protective films 17 and 19 having alkali resistance made of, for example, are formed, the surface of the metal thin film 18 is not directly immersed in the developing solution during the development of the resist film, and the incidence of defects is reduced. In addition, since the contact portion between the transparent electrode film 16 and the metal thin film 18 is not exposed to the developing solution, it is possible to prevent electrolytic corrosion of the transparent electrode film 16 and thereby the display defect occurrence rate. Can be significantly reduced. Furthermore, the protective films 17, 19 of this embodiment
Since the surface light reflectance of Mo etc. used as the material of is extremely lower than that of Al, it is possible to minimize the effect of scattered light due to surface protrusions during resist exposure, further reducing the defect occurrence rate of wiring. be able to.
なお、以上の実施例では保護膜の材料としてMoを用いた
ものについて説明したが、この他にたとえばCr、Tiある
いはＷ等もAlよりも光の表面反射率の小さい耐アルカリ
性の材料であることから保護膜に用いることが可能であ
る。In the above examples, the case where Mo is used as the material of the protective film has been described, but in addition to this, for example, Cr, Ti, W or the like is also an alkali resistant material having a smaller surface reflectance of light than Al. Can be used as a protective film.
［発明の効果］ 以上説明したように本発明によれば、金属薄膜上に保護
膜を形成したので、前記金属薄膜が直接現像液にさらさ
れることがなくなり、配線の不良発生率を大幅に低減さ
せることが可能となる。[Effects of the Invention] According to the present invention as described above, since the protective film is formed on the metal thin film, the metal thin film is not directly exposed to the developing solution, and the defect occurrence rate of the wiring is significantly reduced. It becomes possible.
第１図は本発明の一実施例の配線の形成方法を説明する
ための各主要工程ごとの断面図、第２図は本発明の他の
実施例を説明するための各主要工程ごとの断面図であ
る。 １、11……絶縁基板 ２、18……金属薄膜 ３、17、19……保護膜 ４、20……ポジレジスト膜FIG. 1 is a sectional view of each main step for explaining a wiring forming method according to an embodiment of the present invention, and FIG. 2 is a sectional view of each main step for explaining another embodiment of the present invention. It is a figure. 1, 11 ... Insulating substrate 2, 18 ... Metal thin film 3, 17, 19 ... Protective film 4, 20 ... Positive resist film
Claims (6)
トを用いたエッチングにより所望パターンの配線を形成
する方法において、前記基体上に金属薄膜を着膜した
後、この金属薄膜上に保護膜を着膜し、この保護膜とと
もに前記金属薄膜を前記エッチングにより選択的に除去
して前記配線を形成することを特徴とする配線の形成方
法。1. A method for forming a wiring having a desired pattern from a metal thin film deposited on a substrate by etching using a resist, after depositing the metal thin film on the substrate, and then protecting the metal thin film. A method of forming a wiring, comprising depositing a film, and selectively removing the metal thin film together with the protective film by the etching to form the wiring.
を特徴とする特許請求の範囲第１項記載の配線の形成方
法。2. The method for forming a wiring according to claim 1, wherein the protective film has alkali resistance.
である特許請求の範囲第１項記載の配線の形成方法。3. The method for forming a wiring according to claim 1, wherein the metal thin film is made of aluminum.
ものである特許請求の範囲第１項記載の配線の形成方
法。4. The method for forming a wiring according to claim 1, wherein the metal thin film is made of an aluminum alloy.
射率が小さい他の金属薄膜からなることを特徴とする特
許請求の範囲第１項記載の配線の形成方法。5. The method of forming a wiring according to claim 1, wherein the protective film is made of another metal thin film having a light reflectance lower than that of aluminum.
ムまたはタングステンからなることを特徴とする特許請
求の範囲第５項記載の配線の形成方法。6. The wiring forming method according to claim 5, wherein the protective film is made of molybdenum, titanium, chromium or tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19165287A JPH0760928B2 (en) | 1987-07-31 | 1987-07-31 | Wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19165287A JPH0760928B2 (en) | 1987-07-31 | 1987-07-31 | Wiring formation method |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16045496A Division JP2804253B2 (en) | 1996-06-03 | 1996-06-03 | Electronic device |
| JP16045396A Division JP2774791B2 (en) | 1996-06-03 | 1996-06-03 | Electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6436097A JPS6436097A (en) | 1989-02-07 |
| JPH0760928B2 true JPH0760928B2 (en) | 1995-06-28 |
Family
ID=16278217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19165287A Expired - Lifetime JPH0760928B2 (en) | 1987-07-31 | 1987-07-31 | Wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760928B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6224510B2 (en) | 2014-04-18 | 2017-11-01 | マクセルホールディングス株式会社 | Whisk |
-
1987
- 1987-07-31 JP JP19165287A patent/JPH0760928B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6224510B2 (en) | 2014-04-18 | 2017-11-01 | マクセルホールディングス株式会社 | Whisk |
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