JPH0761064B2 - Digital terminal station receiver - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital terminal station device in a PCM transmission system, and more particularly to a timing extraction circuit in a digital terminal station receiver device for transmitting information at a high speed of about Gb / s. Regarding the improvement of the feasibility of.

(Prior Art) With the progress of optical transmission technology, studies on ultra-high-speed optical transmission technology using long-wavelength band optical devices / single-mode fibers have been promoted as the possibility of large-capacity / long-distance transmission systems.
In particular, in order to realize a broadband information communication network that provides a wide variety of services for images, data, and voice, it is expected that the optical transmission device will operate at high speed and be put into practical use. The transmission capacity of the backbone transmission system in such a broadband information communication network reaches several gigabits / second in a time division multiplex transmission system, for example, and the optical transmitter / receiver is required to have a wide band / high speed.

Usually, a digital terminal device is provided with a transmitting / receiving transmitting device having the same function as that of a regeneration repeating device (for such a transmitting / receiving transmitting device, for example, "F-400M system terminal device repeating device Design and characteristics "Research Practical Report Vol. 32, No. 3, (1983) P-23).

FIG. 2 shows a typical configuration of a conventional digital terminal receiving device. Here, the 1: 2 conversion is shown as an example of the serial / parallel conversion function. In the reception device 201, the reception signal received from the transmission system is used to extract a clock signal and identify and reproduce the reception signal using the clock signal, as in a normal intermediate reproduction relay device. The data reproduced and identified by the receiving device 201 and the extracted clock signal are transferred to the serial / parallel converter 20.
2 (also called “demultiplex conversion”). In the serial / parallel conversion unit 202, the clock signal input from the reception device 201 has a 1/2 cycle and a phase of 180 ° which are necessary to perform 1: 2 serial / parallel conversion in the 1/2 divider circuit 2023. Converted to the shifted two-phase clock signals. Further, the two-phase clock signals are respectively supplied to the latch circuits 2021 and 2022 which perform serial / parallel conversion. On the other hand, the reception signal identified and reproduced by the identification circuit 2011 of the reception device 201 is branched into two and input to the latch circuits 2021 and 2022 of the serial / parallel conversion unit 202, and the 1/2 frequency division circuit is input.
With the clock signal supplied from 2023, 1CH of the serial 2CH signals time-division multiplexed at the transmitting side is latched and output to each output terminal.

The receiving device 201 is provided with a timing circuit 2012 which has a role of giving a time point at the center of the eye in order to make a correct discrimination with respect to the equalized waveform. Generally, in the case of a PCM transmission system, the transmitted code sequence itself is included. A timing extraction circuit is used to extract a timing component from among the above.

FIG. 3 is a block diagram showing the configuration of a conventional timing extraction circuit. The code format of the input signal is assumed to be NRZ code. Since the NRZ code, the bipolar code, and the like do not have a timing component themselves, generally, a timing signal is extracted by a non-linear timing extraction method to generate a clock signal.

In FIG. 3, the sign change point detection is performed by the differentiating circuit 301 for the NRZ signal input to the input terminal 1, and the differentiating circuit 3
About 01 of the output signal f _o component-wave rectified by full-wave rectifying circuit 302 is is the basic frequency applied is extracted. The output signal of the full-wave rectifier circuit 302 is applied to the resonant circuit (timing tank) to be, f _o sinusoidal components (clock signal) is extracted. As the resonance circuit, since the timing deviation is regarded as an important characteristic, a surface acoustic wave filter (SAW) 303 having a relative band Q of about 800 is used in consideration of temperature characteristics, aging, detuning and the like. (For details on SAW filters, see "Surface Wave Devices and Their Applications", Nikkan Kogyo Shimbun). On the other hand, when the code format of the input signal is RZ, since the signal itself has a clock component, the RZ signal received at the terminal 9 is directly applied to the surface acoustic wave filter 303 as shown by the broken line in FIG. Extract the clock signal.

(Problems to be Solved) However, in the receiving apparatus in such a prior art digital terminal station receiving apparatus, the clock signal extracted by the frequency f _o in synchronization with the data transmission rate using a SAW filter having a high Q Since the serial / parallel conversion unit performs signal processing for dividing the frequency by 1 / N, the characteristics of the clock signal are deteriorated.
In addition, a surface acoustic wave filter is used as a timing extraction circuit in the receiving device, that is, a timing tank, and
The format to be generated directly clock signal f _o component in the z-domain, to a limit to the frequency domain that can be used from the micro-processing problems of surface acoustic wave filters, there is a problem that the yield of the process is low, which Sufficient productivity cannot be obtained for PCM signal receivers using the.

That is, the fundamental frequency f of the surface wave excited in the surface acoustic wave filter is f = V / L depending on the surface wave propagation velocity V of the material and the electrode pitch L. Therefore, when the excitation frequency is in the CHz region, the surface wave propagation velocity is generally 3 × 10 ₃
Since it is (m / s), the electrode width must be 1 μm or less. As a specific example, the electrode width of the surface acoustic wave filter used in the 4 Gbps optical regenerator is 0.2 μm using a quartz substrate as the material and 400 μm as the electrode length.
(“Prototype of 4 Gbps optical regenerator”, Institute of Electronics, Information and Communication Engineers, 1987 General National Conference Proceedings). Fabrication of such a highly accurate surface acoustic wave filter with a lightning pole width is difficult due to limitations in processing technology such as photo-etching and laser processing, and eventually the timing extraction circuit of the PCM signal receiver in the Gbps region is difficult. It cannot be realized. As described above, in the conventional digital terminal receiving device, it is difficult to realize the timing extraction circuit in the high frequency region, and it remains as a problem to be solved.

(Means for Solving the Problems) Means provided by the present invention for solving the above problems are
What is claimed is: 1. A digital terminal station receiver for identifying and reproducing a received signal and further converting the signal in parallel / parallel, comprising: a first timing extraction filter for extracting a basic timing component from the input received signal; and a first timing A frequency dividing circuit for dividing the output signal of the extraction filter into 1 / N (N is an integer of 2 or more), and a second timing for extracting a stable timing signal of 1 / N frequency from the output signal of the frequency dividing circuit. An extraction filter, a clock distribution circuit for generating and distributing a clock signal of N phase and 1 / N frequency from the timing signal of 1 / N frequency extracted by the second timing extraction filter, and the clock distribution circuit of 1 / N frequency And a serial / parallel conversion circuit for simultaneously performing the identification reproduction of the received signal and the serial / parallel conversion with a clock signal.

(Operation) In the present invention, a coarse timing component is extracted from an input signal, the coarse timing component is divided into a frequency region of 1 / N, a clock signal is generated by a highly stable timing tank, and the clock signal is generated. By supplying the serial / parallel converter and omitting the identification circuit in the receiving device and using the latch circuit of the serial / parallel converter in common, the GHz
It is possible to improve the feasibility of the timing extraction circuit in the area, avoid the characteristic deterioration of the clock signal, and reduce the device scale.

(Example) The Example of this invention is described with reference to drawings.

FIG. 1 is a block diagram showing the configuration of a digital terminal station receiver which is an embodiment of the present invention. In the following description, RZ (return to
(Zero) code is assumed.

The RZ reception signal input to the input terminal 100 is sufficiently amplified by the amplifier 101 and then applied to the latch circuits 2021 and 2022 and the first timing extraction filter 102. The first timing extraction filter 102 extracts a clock signal synchronized with the frequency f _o from the input RZ reception signal with coarse accuracy. Therefore, the timing tank to be used may be a filter having a ratio band Q that can extract a clock signal that does not affect the amount of timing jitter (approximately
500 or less). The clock signal of the coarse f _o component extracted by the first timing extraction filter 102 is counted down by the 1 / N frequency divider 103 at an arbitrary frequency division ratio. This divider circuit
As the frequency division ratio of 103, a ratio matching the time division multiplicity N is used. Clock signal f divided by 1 / N by 1 / N divider 103
_o / N is input to the second timing extraction filter 104. In the second timing extraction filter 104, to set the center frequency f _o / N, the timing deviation, it is necessary to set such a high specific band Q in consideration of detuning. In particular, it is desirable to use a surface acoustic wave filter (SAW filter) as a timing tank in consideration of secular change and temperature characteristics.

Now in FIG. 1, the frequency f _o of the basic timing component is
4 GHz, when the frequency division ratio 8, f _o / N becomes 500 MHz. Second
If the timing extraction filter 104 is a surface acoustic wave filter made of quartz, the surface acoustic wave wavelength is about 6.3 μm.
Is. If the strip width and the gap of the interdigital electrode are selected to be equal, the strip width is about 1.6 μm, and such an electrode pattern can be easily formed by a normal photo-enching technique.

The clock signal of f _o / N having stable characteristics extracted by the second timing extraction filter 104 is the clock distribution circuit 10
Supplied to 5. In this clock distribution circuit 105, the number of serial / parallel conversions, that is, N phases, is T /
Clock signals that are shifted by N (T: one cycle time) are generated and supplied to the latch circuits 2021 and 2022, respectively. Latch circuit 2021,2022
Latches the received signals respectively inputted by this clock signal and outputs them. Therefore, at this stage, the received signal identification processing and the serial / parallel conversion processing are simultaneously satisfied.

In the present invention, as in the embodiment of FIG. 1, the high-Q surface acoustic wave filter necessary for performing timing extraction is used in the region of 1 / N frequency division ratio. The feasibility of the timing extraction circuit is improved, and a stable clock signal can be supplied to the serial / parallel conversion circuit.

In the above description, the case where the code format of the received signal is RZ has been described, but the present invention is also effective in the case of NRZ, and the differentiating circuit 30 as in the conventional example shown in FIG.
1. After passing through the non-linear means of the both-wave rectification circuit 302, the same function can be obtained by connecting to the input terminal 9 of FIG.

(Effect of the Invention) As described in detail above with reference to the embodiments, by using the digital terminal receiving apparatus according to the present invention, the feasibility of the timing extraction circuit in the high-speed PCM signal transmission system and the stabilization of the serial / parallel conversion function It is possible to improve the simplification of the device configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a conventional digital terminal receiving apparatus, and FIG. 3 is a detail of a timing extraction circuit in the apparatus of FIG. It is a block diagram showing. 100,1,9 ... input end, 4 ... output end, 301 ... differential circuit, 302 ...
Double-wave rectification circuit, 303 ... Surface acoustic wave filter, 102 ... First timing extraction filter, 103 ... 1 / N frequency dividing circuit, 104 ... Second timing extraction filter, 105 ... Clock distribution circuit, 101 ... Amplification circuit, 201 ... Receiving device, 202 ... Serial / parallel conversion circuit, 2011 ... Identification circuit, 2012 ... Timing extraction circuit,
2021,2022 ... Latch circuit, 2023 ... 1/2 divider circuit.

Claims (1)

[Claims] 1. A digital terminal station receiver for identifying and reproducing a received signal and further serial / parallel exchanging the signal, a first timing extraction filter for extracting a basic timing component from the input received signal, and the first timing extraction filter. Output signal of 1 timing extraction filter is 1 / N (N is an integer of 2 or more)
A frequency dividing circuit, a second timing extracting filter for extracting a stable timing signal of 1 / N frequency from an output signal of the frequency dividing circuit, and a 1 / n extracted by the second timing extracting filter. A clock distribution circuit that generates and distributes an N-phase 1 / N frequency clock signal from an N-frequency timing signal, and simultaneously performs the identification reproduction and the serial / parallel conversion of the received signal with the 1 / N frequency clock signal. A digital terminal receiving device comprising a serial / parallel conversion circuit for performing the conversion.