JPH0834463B2 - Timing extraction circuit - Google Patents

Description

The present invention relates to a timing extraction circuit, and more particularly to a timing extraction circuit of a receiver in a transmission system that transmits information of several gigabits / second.

[Conventional technology]

With the progress of optical transmission technology, studies on ultra-high-speed optical transmission technology using long-wavelength band optical devices and single-mode optical fibers are being pursued as a possibility for large-capacity, long-distance transmission systems, especially for images and data. -In order to realize a wideband information communication network that provides a wide variety of voice services, it is expected that optical transmission equipment will operate at high speed and be put into practical use. The transmission capacity of the backbone transmission system in such a broadband information communication network reaches, for example, several gigabits per second in a time division multiplex transmission system, and the optical transmitter / receiver is required to have a wide band and high speed.

Normally, the receiver of the transmission device is equipped with a timing circuit that serves to give the time point at the center of the eye in order to make a correct identification for the equalized waveform. Generally, in the case of PCM reproduction relay, it is transmitted. A timing extraction circuit that extracts a timing component from the code sequence itself is used.

FIG. 2 is a block diagram of an example of a conventional timing extraction circuit.

Assume that the code format of the input signal is an NRZ code. NRZ
Since a code or a bipolar code does not have a timing component in the signal itself, a timing signal is generally extracted by a non-linear timing extraction method to generate a clock signal.

In FIG. 2, the NRZ signal input to the input terminal 1 is subjected to sign change point detection in the differentiating circuit 2 and double-wave rectified in the double-wave rectifying circuit 3 to extract the clock component of frequency f ₀ . The output signal 3 of the double wave rectification circuit 3 is further applied to the resonance circuit (timing tank),
The sine wave component (clock signal) of f ₀ is extracted. Since the timing deviation is important as an important characteristic of the resonance circuit, the surface acoustic wave filter 4 (see “Surface wave”) is designed to have a relative bandwidth Q of about 800 in consideration of temperature characteristics, aging, detuning, etc. The device and its application "Nikkan Kogyo Shimbun" are used.

On the other hand, when the code format of the input signal is RZ, since the signal itself has a clock component, the RZ signal input to the input terminal 5 is directly applied to the surface acoustic wave filter 4 to extract a sine wave clock signal.

[Problems to be Solved by the Invention]

However, in such a conventional timing extraction circuit format, that is, a format in which a surface acoustic wave filter is used as a timing tank to directly generate a clock signal of a frequency in the GHz range, there is a problem in fine processing of the surface acoustic wave filter. There is a problem that the usable frequency range is limited and the process yield is reduced, which leads to a reduction in the productivity of the PCM signal receiver using this.

That is, the fundamental frequency f of the surface wave excited in the surface acoustic wave filter is determined by the surface wave propagation velocity V of the material and the electrode pitch L, and f = V / L. Therefore, when the excitation frequency is in the GHz range, the surface wave propagation velocity L is generally about 3 × 10 ³ m / s, so that the electrode width must be 1 micron or less. As a specific example, the electrode width of the surface acoustic wave filter used in the 4 Gbps optical regenerator is 0.2 micron using a quartz substrate as the material and 400 micron as the electrode length (Reference: 1987 General National Convention Proceedings) "Prototype of 4Gbps optical regenerator" IEICE.

In order to accurately process such an electrode width, there is a limit in processing technology such as photo etching and laser processing, so it is difficult to realize a surface acoustic wave filter, and Gbps
There is a big problem that the timing extraction circuit of the PCM signal receiver in the area cannot be realized.

[Means for solving the problem]

The timing extraction circuit of the present invention is a timing extraction circuit of a PCM signal receiver including a tank circuit for inputting a reception signal and outputting a clock signal, the first timing extraction for extracting a coarse timing component from the input reception signal. A filter, a frequency dividing circuit for dividing the output signal of the first timing extraction filter into 1 / N, a second timing extraction filter for extracting a stable timing signal from the output signal of the frequency dividing circuit, And a multiplication circuit for multiplying the timing signal extracted by the second timing extraction filter by N times.

[Action]

Extracting a coarse timing component from the input signal, dividing this coarse timing component into a frequency range of 1 / N, generating a clock signal with a highly stable timing tank, and multiplying this clock signal by N. As a result, the feasibility of the timing extraction circuit in the GHz region can be improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

Now, it is assumed that the code format of the reception equalization waveform is the RZ code.

The RZ signal input to the input terminal 5 is applied to the first timing extraction filter 11. The first timing extraction filter 11 extracts a clock signal synchronized with the clock frequency f ₀ from the equalized waveform of the input RZ signal with coarse accuracy. Therefore, the timing tank to be used may be a filter having a ratio band Q capable of extracting a clock signal that does not significantly affect the amount of timing jitter (Q is about several hundreds). The clock signal of the coarse f ₀ component extracted by the first timing extraction filter 11 is counted down by the 1 / N frequency dividing circuit 12 at an arbitrary frequency division ratio.
The frequency division ratio of the frequency dividing circuit 12 can be arbitrarily selected to a frequency division ratio to a region where a high Q timing tank can be realized. The clock signal divided into 1 / N by the 1 / N divider circuit 12 is input to the second timing extraction filter 13. The second timing extraction filter 13 needs to have its center frequency set to f ₀ / N, and set to a high specific band Q in consideration of timing deviation, detuning, and the like. Considering aging and temperature characteristics, it is desirable to use a surface acoustic wave filter as the timing tank.

Now, assuming that the clock frequency f ₀ is 4 GHz and the division ratio N is 8, f ₀ / N is 500 MHz. When the second timing extraction filter 13 is a surface acoustic wave filter made of quartz, the surface acoustic wave wavelength is about 6.3 μm. If the strip width and the gap width of the interdigital electrode are selected to be equal, the strip width is about 1.6 μm, and such an electrode pattern can be formed by a normal photoetching technique.

The clock signal of the frequency f ₀ / N having the stable characteristic extracted by the second timing extraction filter 13 is the N multiplication circuit 14
Thus, the frequency is multiplied by N to the frequency f ₀ synchronized with the RZ signal input to the input terminal 5. Frequency obtained by N multiplication circuit 14
The clock signal at f ₀ usually has harmonic components due to the multiplier circuit. Therefore, the band pass filter 15 removes the harmonic component and the low frequency side noise, and outputs the clock signal of the frequency f ₀ from the output end.

Generally, a limiter amplifier circuit is subordinately connected to the output end of the timing extraction circuit in order to suppress the fluctuation of the clock signal amplitude due to the fluctuation of the mark rate of the code sequence. A similar limiter amplifier circuit is naturally connected to the output terminal of the timing extraction circuit according to the present invention.

The present invention is also effective when the code format of the reception equalized waveform is NRZ, and as shown in FIG. 1, the NRZ signal input to the input terminal 1 does not have a clock component in its spectrum, so that a differentiating circuit is provided. 2. After the clock component of frequency f ₀ is generated by the non-linear means of the both-wave rectification circuit 3, it is input to the first timing extraction filter 11.

〔The invention's effect〕

As described above, according to the present invention, the feasibility of the timing extraction circuit of the high-speed PCM signal transmission system is achieved by using the high-Q surface acoustic wave filter necessary for performing the timing extraction in the region of the 1 / N frequency division ratio. And a stable clock signal can be supplied to the identification circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional timing extraction circuit. 11 ... First timing extraction circuit, 12 ... 1 / N frequency dividing circuit, 13
... second timing extraction circuit, 14 ... N multiplication circuit.

Claims (1)

[Claims] 1. A timing extraction circuit of a PCM signal receiver having a tank circuit for receiving a received signal and outputting a clock signal, comprising: a first timing extraction filter for extracting a coarse timing component from the inputted received signal; A frequency divider circuit that divides the output signal of the first timing extraction filter into 1 / N, a second timing extraction filter that extracts a stable timing signal from the output signal of the frequency divider circuit, and a second timing extraction filter A timing extraction circuit comprising: a multiplication circuit for multiplying the timing signal extracted by the timing extraction filter by N times.