JPH0766313B2 - Inter-processor communication method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication system for transferring data between processors, and more particularly, interprocessor communication in a printer such as a serial dot printer for performing forward direction printing and reverse direction printing. It is related to the method.

(Prior Art) Conventionally, as this type of inter-processor communication method, a method of communicating via a serial port built in the processor, a method of connecting the processors with a bidirectional register, and communicating via the bidirectional register Etc. were commonly used. In the latter method, when one processor writes data to a bidirectional register and notifies the other processor that the data has been written, the other processor receives the notification and reads the data from the bidirectional register. It is a communication system that transfers data by performing the above-mentioned operations bidirectionally.

(Problems to be Solved by the Invention) However, in any of the above communication systems, the processor needs to write or read each byte, and thus print data (image data) to be transferred between processors like a printer. When the data amount of () is large, most of the processing time of the processors is used for data transfer between the processors, so that there is a problem that the data processing efficiency of the processors is significantly reduced. Further, the receiving side (slave) processor needs to edit the received data according to the amount of data such as the number of elements of the print head that prints at once, and the printer that performs forward direction printing and reverse direction printing Since it is necessary to rearrange the data according to the direction, there is a problem that the processing load on the receiving side processor is heavy.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above problems, improve the data processing efficiency of a processor, and provide an interprocessor communication system that can reduce the burden on the processor on the receiving side.

(Means for Solving the Problem) In order to solve the above problems, the present invention relates to an interprocessor communication system for transferring data between a first processor and a second processor, and stores data accessed by a first processor. And a memory connected in parallel to the output of the memory and the number of stages is determined according to the amount of data to be printed at one time.
Stage register, a selector for selecting an output of the m-stage register based on a selection signal, a write timing for the m-stage register based on a write signal from the first processor, and a second processor Generating means for generating the selection signal based on the read signal from
By controlling one of the write timing and the timing of the selection signal based on a mode signal indicating whether the first-in / first-out first mode is the first-in / stout second mode,
In the case of printing in the forward direction, the mode signal is set to the first mode when the printing is performed in the forward direction. In the mode 1, the first and the processor read the contents of the memory at ascending addresses, read the contents of the memory at descending addresses when printing in the reverse direction, and give a write signal to the generating means. Then, the second processor writes the data to the m-stage register, and the second processor reads the contents of the m-stage register through the selector by giving a read signal to the generating means.

(Operation) The present invention operates as follows. The amount of data printed at one time, for example, the number of print head elements printed at one time
When it is 16, 2 bytes (= 16/8) are set, and two stages of registers (first stage and second stage registers) are provided, and writing and reading are performed continuously for 2 bytes. That is, in the case of printing in the forward direction, for example, the first and the processor give the mode signal as the first mode to the setting means, and then continuously read the contents of the memory for 2 bytes at the ascending order of the addresses and read the contents of 2 bytes.
The write signal is sent to the register of the stage and the write signal is given to the generating means. As a result, generating means (for example, a counter described later,
The duder and the output gate circuit, etc.) generate the write timing of the two-stage register based on the write signal. The setting means (for example, a mode setting circuit described later) sets the mode by controlling the write timing generated by the generating means or the timing of the selection signal. For example, when controlling the write timing, when the generating means generates the write timing in the order of the first-stage register and the second-stage register based on the write signal, the setting means keeps the write timing as it is in the first mode. Is given to the corresponding register in the second mode, and the write timing is given to the two-stage register in the reverse order of the second-stage register and the first-stage register in the second mode. In the case of printing in the forward direction, since it is the first mode, the data of the first byte is set in the register of the first stage and the data of the second byte is set in the register of the second stage. On the other hand, when the second processor gives a read signal to the generating means, the generating means causes the selector to generate a selection signal for selecting its output in the order of the first stage register and the second stage register. As a result,
The contents of the registers of the first stage and the second stage are read continuously for 2 bytes. Therefore, the read data can be printed in the forward direction without editing the data on the second processor side. On the other hand, in the case of reverse direction printing, for example, the first processor sends the mode signal to the second signal.
Mode, the contents of the memory are continuously read for 2 bytes at the addresses in descending order and sent to the registers of two stages. In the second mode, as described above, the setting means controls the write timing in reverse, so that the data of the first byte is set in the register of the second stage and the data of the second byte is the first. It is set in the stage register. Therefore,
The second processor sets the selector in the order of the data of the second byte set in the register of the first stage and the data of the first byte set in the register of the second stage in the same manner as in the case of printing in the forward direction. Can be read through.
Therefore, since the data is edited and rearranged at the time of data transfer, the second processor can perform reverse direction printing without performing these processes. Therefore, it is possible to solve the problems of the prior art.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 (a) is a block diagram showing an embodiment of the present invention. In the figure, 1 is a master processor (CPUA),
2 is a ROM that stores the program executed by CPU A1 and 3 is a CP
RAM for storing data (print data) processed by UA1, 4
Is a register unit for storing data to be transferred, 5 is a register control unit for controlling the register unit 4, 6 is a slave processor (CPUB), 7 is a ROM for storing a program executed by the CPUB6, and 8 is a process of the CPUB6. RAM to store data
Is. As shown in FIG. 3A, the CPUA1 is moved to the ROM2, RAM3 and the input of the register unit 4 by the data bus of the CPUA1, and the CPUA1 is connected to the ROM2 and RAM3 at the address of the CPUA1. On the other hand, the CPUB6 and the register unit 4, ROM7 and RAM8 are connected by the data bus of the CPUB6.
B6 is connected to ROM7 and RAM8 by the address bus of CPUB6. A drive circuit (not shown) for the print head is connected to the data bus of the CPUB6.

FIG. 1B is an internal configuration diagram of the register unit 4 and the register control unit 5. FIG. 1B shows the configuration in the case of a printer in which the print head has 24 elements.

In the register unit 4, since the print head is composed of 24 elements, the register 24 that stores the data to be transferred
[Elements] / 8 [bits] = 3 [bytes]. 3 bytes (that is, 3 rows) as shown in FIG.
Register (# 1) 41, register (# 2) 4
2 and register (# 3) 43. Each of the registers 41 to 43 is composed of eight D flip-flops (DF / F).
The inputs of the registers 41 to 43 are connected to the data bus from the CPU A1, and the outputs are connected to the data bus of the CPU B6 through the selector 44 that selects the output data of the registers 41 to 43.

The register control unit 5 is composed of a NOR gate 50, a counter 51, a decoder 52, a mode setting circuit 53, an output gate circuit 54, and a state notification circuit 55, as shown in FIG. The portion composed of the NOR gate 50, the count 51, the decoder 52 and the output gate circuit 54 corresponds to the above-mentioned generating means, and the mode setting circuit 53 corresponds to the setting means.

The counter 51 is a ternary counter including D flip-flops (DF / F) 51a and 51b and a NOR gate 51. The count input (that is, clock terminal) of this counter 51 is CP
Register write signal (register WR) from UA1 and register read signal (register RD) from CPUB6 are NOR gates
It is input as a clock signal (▲▲) by Noah condition by 50. This counter 51 is register WR or register
Count up in the order of "01", "10", "00"("MSBLSB") by RD. The MSB is the DF / F51a Q _A output, LSB
Indicates the Q _A output of DF / F51b. Further, the Q _A output of DF / F 51a and 51b becomes the selection signal of the selector 44.

The decoder 52 is composed of NOR gates 52a, 52b and 52c, and decodes the output of the counter 51 into a state of "00" by the NOR gate 52a, "01" by the NOR gate 52b and "10" by the NOR gate 52c. In other words, "00" indicates when the Q _A output of the DF / F51a is logic "0" and the Q _A output of the DF / F51b is logic "0".
At this time, the output of the NOR gate 52a becomes a logic "1". In addition, “01” means that the Q _A output of DF / F51a is logic “0”, and Q _{A of} DF / F51b is
Indicates when the output is logic "1", at which time NOR gate 52b
The output of is a logical "1". Furthermore, "10" is Q of DF / F51a
_{The A} output is logic "1" and the Q _A output of the DF / F 51b is logic "0". At this time, the output of the NOR gate 52c is logic "1".

The mode setting circuit 53b includes an inverter 53a and an AND gate 53.
b-53e, and OR gates 53f, 53g, by controlling the output (write timing) of the decoder 52 based on the mode signal from the CPUA1, the first in / first out mode (mode signal "H"), Set the first-in / last-out mode (mode signal “L”).

The output gate circuit 54 includes three NAND gates 54a, 54b, 54c.
And the register WR is gated by each gate based on the output of the mode setting circuit 53, and the register # 1 write pulse signal is supplied to the registers 41 to 43, respectively. Register # 2 write pulse signal Register # 3 write pulse signal give.

The status notification circuit 55 is composed of NAND gates 55a and 55b and an SR flip-flop (SRF / F) 55c. The state notification circuit 55 sets the register WR to the NAND gate 5 based on the output of the NOR gate 52c of the decoder 52.
5a and the register RD are gated by the NAND gate 55b, respectively, and these are inputted to the set (S) input terminal and the reset (R) input terminal of the SRF / F55c, respectively.
A register full signal is output to 6 and a register empty signal is output to CPUA1.

Next, the control operation of the register control unit 5 with respect to the register unit 4 will be described with reference to the time charts of FIGS. FIGS. 11A and 11B are time charts in the first-in / first-out mode and the first-in / last-out mode, respectively.

The data writing from the CPU A1 to the registers 41 to 43 of the register unit 4 and the data reading from the CPU B6 are performed in units of 3 bytes.

First, the case of writing will be described. In order to write transfer data continuously for 3 bytes, the register WR from the CPUA1 is used as the register WR, and the pulse of the first byte write signal W1, the second byte write signal W2, and the third byte write signal W3 is NOR gated. It is sequentially input to the ternary counter 51 via 50, and the counter 51 counts up in the order of "01", "10", "00" (Fig. 2 (a), (c)). Each output of the counter 51 (that is, Q _A of the DF / F 51a, 51b, ∇ output) is decoded by the NOR gates 52a, 52b, 52c of the decoder 52. That is, as explained earlier regarding the operation of the NOR gates 52a, 52b, 52c, when the Q _A output of the DF / F51a is logic “0” and the Q _A output of the DF / F51b is logic “0”, the output of the NOR gate 52a is Logical "1", D
When the Q _A output of the F / F51a is logic “0” and the Q _A output of the DF / F51b is logic “1”, the output of the NOR gate 52b becomes logic “1”, and DF /
F 51a Q _A output is logic “1”, DF / F51b Q _A output is logic “0”
At this time, the output of the NOR gate 52c becomes a logic "1" (Fig. 2 (d)). The output signals of the NOR gates 52a to 52c of the decoder 52 are directly sent to the output gate circuit 54 via the mode setting circuit 53 in the first-in / first mode (mode signal "H"). That is, as shown in FIG. 1 (b), the output signal of the NOR gate 52a is transmitted through the AND gate 53c and the OR gate 53f to the NAND gate 54a and the NOR gate 52b.
The output signal of the AND gate 53e and the OR gate 53 are the output signals of the NAND gate 54b and the NOR gate 52c which are directly connected.
It is sent to each one input terminal of the NAND gate 54c via g. On the other hand, at the time of first-in / last-out (mode signal "L"), the output signal of the NOR gate 52a passes through the AND gate 53d and the OR gate 53g.
c and one input terminal, and the output signal of the NOR gate 52c is sent to one input terminal of the NAND gate 54a via the AND gate 53b and the OR gate 53f. As a result, according to the timing of W1, W2, W3 of the register WR input to the other input terminals of the NAND gates 54a, 54b, 54c of the output gate circuit 54, in the first-in / first-out mode. In first-in / last-out mode Registers (# 1) 4 from NAND gates 54a, 54b, 54c in this order
1, these corresponding signals are supplied to the register (# 2) and the register (# 3) 43 (Fig. 2 (e) (f))
(G)). Therefore, in the first-in / first-out mode, the write data of the first byte is written in the register (# 1) 41, the data of the second byte is the register (# 2) 42, and the data of the third byte is register(#
3) Written at 43. In the first-in / last-out mode, the data of the first byte is the register (#
3) 43, the data of the second byte is the register (# 2) 42
Then, the data of the third byte is written in the register (# 1) 41. When the writing of 3 bytes of data is completed in this way, the register write signal (register
WR) indicates that the output of the counter 51 is "10", that is, the Q _A output of DF / F51a is logic "0", and the output of the NOR gate 52c is logic "1" when the Q _A output of DF / F51b is logic "1". As a result, it is gated by the NAND gate 55a, sets the SRF / F 55c, and stores the register full state (FIG. 2 (h)). SRF / F55c
Then, the Q output is input to the CPUA1 and the CPUB6, the CPUA1 is notified that the data has been written in the registers 41 to 43, and the CPUB6 is notified that the data is present in the registers 41 to 43.

Next, the case of reading will be described. First as register RD from CPUB6 to read 3 bytes of data continuously
Read signal R1 of the second byte, read signal R of the second byte
The pulse of the read signal R3 of the 2nd and 3rd bytes is a ternary counter via the NOR gate 50 in the same way as in the case of writing.
It is input to 51 and cut up. As described above, the data written in the registers 41 to 43 from the data bus of the CPU A1 is output to the selector 44, where it is selected based on the selection signal. By the selection signal (select) of the selector 44, the output of the ternary counter 51 (that is, DF / F51
The Q _A output (MSB) of a) and the Q _A output (LSB) of DF / F51b are “0”.
The register (# 1) 41 is selected when it is "0", the register (# 2) 42 when it is "01", and the register (# 3) 43 when it is "10" (Fig. 2 (a) (b) ( Therefore, the data from the register (# 1) 41 is read at the timing of R1 of the register RD, and similarly, the data of the registers (# 2) 42 and (# 3) 43 is read at the timing of the pulses of R2 and R3. Each data is read and output to the data bus of CPUB6.
Reading of data from 3 is always performed in the order of the registers # 1, # 2, # 3 in both the first-in / first-out mode and the first-in / last-out mode.

Next, forward direction (FOW) printing and reverse direction (RE
V) The transfer operation between the processors in the case of printing will be described with reference to the flowchart of the data transfer of the CPU A1 in FIG. 3 and the explanatory diagram in FIG. 4A and 4B show the case of the first-in / first-out mode and the first-in / last-out mode, respectively.

First, prior to the start of printing, the CPU A1 sets the mode signal to "H" and sets the first-in / first-out mode when printing in the forward direction.

Next, it is checked whether or not the registers 41 to 43 are empty by the output signal of the status notification circuit 55 of the register control unit 5. If the empty, that is, the transfer data is read to the CPU B6, the process proceeds to the next step, and if not empty. ,
That is, if the transfer data remains in the register, it waits until the register becomes empty (S1). The output signal (register empty signal) of the status notification circuit 55 is the register 41 to 43.
In the case of the empty state, the print direction is checked, and if the print is in the forward direction, the process proceeds to S3. If the print is in the reverse direction, the process proceeds to S10 (S2). In this case, since the printing is in the forward direction, the processes after step S3 are performed.

That is, first, the CPUA1 extracts the data of the first byte from the address of the RAM3 as the data memory indicated by the address pointer indicating the storage destination of the transfer data in the CPUA1 on the RAM3, and outputs the register write signal (register WR). The data of the first byte is written to the register (# 1) 41 of the register unit 4 by giving it to the register control unit 5 (S3). For example, in FIG. 4A, 1-byte data A1 at address m is set in the register 41. After that, the address pointer is incremented (+1) to prepare the extraction destination of the next data (S4). The address of RAM3 indicated by the incremented address pointer (m in FIG. 4 (a)
Data of the second byte from +1) (A in FIG. 4 (a))
2) Take out the register (#
2) After setting the second byte of data in 42, increment the address pointer (S5, S6). Similarly, the data of the third byte (m + 3 of FIG. 4A)
A3) is fetched from RAM3, set in register (# 3) 43, and the address pointer is incremented (S7, S
8).

As described above, the empty state of the register is checked every 3 bytes under the control of CPUA1.
Write to registers 41 to 43 consecutively. Figure 4 (a)
In the example, the ascending address of RAM3 m, m + 1, m + 2, ..., m +
n-2, m + n-1, m + n data A1, A2, A3, ..., Z1, Z2, Z3
Is written in registers 41 to 43 in 3-byte units. CPUB6
Checks the output signal (register full signal) of the status notification circuit 55 of the register control unit 5,
In the case of indicating the full state of 43, a register read signal (register RD) is sent to the register control unit 5, and the registers 41 to 43 are sent.
The data is read in 3-byte units via the selector and sent to the drive circuit of the print head. That is, as shown in FIG. 4 (a), A1, A2, A3, B1, B2, B3, ... Z1, Z2, Z3 are read in 3-byte units in this order, and the 3-byte data of A1, A2, A3 is read. Is sent to the drive circuit of the print head via the data bus without the CPUB6 editing the 3-byte data of Z1, Z2, Z3 as the print data (image data) of the K-th column. The head prints in the forward direction.

When printing in the reverse direction, CPUA1 sets the mode signal to "L" in the first-in / last-out mode and decrements the address pointer (-1), that is, the data in RAM3, before starting printing. The same processing as in the case of printing in the forward direction is performed except that is read in descending order of addresses (S1, S2, S10 to S15). The reading by CPUB6 is the same as the case of printing in the forward direction.

That is, as shown in FIG. 4 (b), m + n, m + n of RAM3
The corresponding data Z3, Z2, Z1, ..., A3, A2, A1 is read in 3-byte units from the addresses in descending order of -1, m + n-2, ... m + 2, m + 1, m, and Z1 is stored in registers 41 to 43. Set as Z2, Z3, ..., A1, A2, A3. Under the control of CPUB6, these are read in 3-byte units and Z1, Z2, Z3 are read in the Kth column, ..., A1, A2, A.
3 is sent as the print data of the first column to the drive circuit of the print head without being edited by the CPU B6, and the print head performs printing in the reverse direction.

In the above embodiments, the mode setting circuit 53 performs the mode setting by controlling the write timing, but the mode setting circuit 53 performs the mode setting by controlling the timing of the selection signal of the selector 44 (that is, the read timing of the register). You may do it. Although the mode signal is supplied from the CPU A1 to the mode setting circuit 53, it may be supplied from the CPU B6 or the like.

As described above, according to this embodiment, the register is set to the first-in / first-out format or the first-in / last-out format depending on the printing direction and the number of stages of the register is set to the number of bytes corresponding to the element of the head. The slave processor 6 may set the data in the drive circuits of the print heads in the order in which they are fetched from the registers 41 to 43, and it is necessary to rearrange the data fetched from the registers 41 to 43 in correspondence with the elements of the print head depending on the printing direction. Is eliminated and the processing throughput of the slave processor 6 is improved. Further, the master processor 1 can continuously write data and the slave processor 6 can continuously read data in units of the number of stages of registers, and both the master / slave processors can empty / full data for each byte. It is not necessary to check and the processing throughput can be improved.

(Effect of the Invention) As described in detail above, according to the present invention, registers of the number of stages determined according to the amount of data to be printed at a time are provided between the processors, and these registers are fast according to the printing direction. By configuring so that the first mode of in / first out and the second mode of first in / last out can be set, the data is edited between the processors according to the output format and the printing direction is different. Since the data is rearranged by the above, the second processor on the receiving side does not need to perform these processes, and the processing load on the second processor is reduced. Further, since the registers can be continuously written and read in units of the number of stages of registers, that is, the number of bytes, the processing efficiency of the processor can be improved.

[Brief description of drawings]

1 (a) and 1 (b) are configuration diagrams showing an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are time charts showing operations of a register unit and a register control unit, and FIG. Flowchart showing the data transfer procedure of CPUA, FIG. 4 (a),
(B) is an operation explanatory view of the present embodiment. 1,6 …… Processor (CPUA, CPUB), 2,7 …… ROM, 3,8 …… RAM, 4 …… Register section, 5 …… Register control section, 41 to 43 …… Register (# 1 to # 3), 44 ... selector, 50 ... NOR gate, 51 ... counter, 52 ... decoder, 53 ... mode setting circuit, 54 ... output gate circuit, 55 ... status notification circuit.

Claims (1)

[Claims] 1. An interprocessor communication system for transferring data between a first processor and a second processor, wherein a memory that is accessed by the first processor to store data, and a memory connected in parallel to the output of the memory to print at one time The number of stages is determined according to the amount of data to be stored, the selector that selects the output of the m-stage register based on the selection signal, and the m-stage register based on the write signal from the first processor Generating means for generating the write timing of the first processor and the selection signal based on the read signal from the second processor, and a first-in / first-out first mode or a first-in / last-out second mode. One of the write timing and the timing of the selection signal is controlled based on a mode signal indicating By,
In the case of printing in the forward direction, the mode signal is set to a first mode when the writing order and the reading order of the m-stage registers are controlled to be the same or opposite to each other. 1 mode, the first processor reads the contents of the memory at ascending addresses, reads the contents of the memory at descending addresses in the case of reverse direction printing, and gives a write signal to the generating means. To write data to the m-stage register, and the second processor reads the contents of the m-stage register through the selector by giving a read signal to the generating means. Inter-communication method.