JPH0766657B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to prevention of signal read error.

[Conventional technology]

FIG. 3 shows an example of a memory cell array structure of a conventional dynamic semiconductor memory device. The memory cell array is divided into two at the Cp point in the bit line direction as shown in the figure. Each of the divided cell arrays is referred to as a sub array (SU
A1, SUA2). Pass bits (TB) are formed alternately in the word line direction in each sub-array. Further, with respect to one bit line, passing bit lines are alternately formed for each sub-array. Here, the passing bit line indicates a bit line in which the bit line and the memory cell are not connected in each sub-array. Further, the passing bit line and the connecting bit line are formed in different wiring layers, and the sub-arrays (area A) are connected to each other. Here, the connecting bit line is a bit line other than the passing bit line, and will be referred to for convenience in order to distinguish it from the main bit line (BL ₀ , ▲ ▼, BL ₁ ...).

Each bit line pair (BL ₀ , ▲ ▼, ...) Has a plurality of memory cell capacitors (Cs) 7 and word line signals (WL ₀ , WL ₀₎ to the gates for connecting the memory cell capacitors 7 and bit lines. ₁
...) is connected to the transfer gate (T _G ) 6. In addition, a dummy cell (DC) 8 for generating a reference level and a dummy word line (DWL ₀ , DWL ₁ ) connecting the bit line to the bit line are connected to each bit line, and the word line rises. After a signal voltage difference appears on the bit line pair, a sense amplifier (SA) 2 for sense-amplifying the bit line potential is connected. Further, a transfer gate (Q) 3 for connecting the bit line pair selected according to the column address to the data input / output line pair (I / 0, ▲ ▼) is provided.

In the conventional structure, since the passing bit and the connecting bit are multi-layered, they can be overlapped with each other, and in the sub-array, almost the same memory cell pitch as that of the open bit line configuration can be realized and the cell array can be made high in density.

Next, the operation will be described. First, let the bit line length in the sub-array divided by Cp points as shown in Fig. 4 be 1 /
Consider the signal voltage on the bit line set to 2. The capacitance of the connecting bit line and the passing bit line with respect to the ground potential through the cell plate or the substrate is C ₀ and C ₁ , respectively, and the capacitance between the connecting bit lines on the same layer that are adjacent via the passing bit line is C ₂ and the bit. The capacitance between the passing bit lines on the same layer
C _3, the capacitance between bit line pairs C _4, the capacitance between the connecting bit lines of adjacent bit line pairs pass bit line and C _5. The memory cell capacity and the dummy cell capacity are Cs. It is assumed that the memory cell stores an electric charge of CsVcc at the H level, the electric charge of 0 at the L level, and the electric charge of 1/2 CsVcc in the dummy cell.

Consider a case where a memory cell connected to the bit line pair BL ₁ is selected. BL1, ▲ ▼ are each ΔVBL1, Δ ▲
It is assumed that only ▼ has changed. Also BL ₁ , ▲
Bit line pair BL ₀ , ▲ ▼, BL ₂ , ▲ adjacent to ▼
▼ is ΔVBL ₀ , ΔV ▲ ▼, ΔVBL ₂ , ΔV ▲
Only ▼ has changed. Bit line BL ₁ , ▲ ▼
Is precharged to a voltage of Va. Bit line BL1, ▲ ▼ voltage VBL ₁ , V ▲ ▼ Is. As a result, the bit line voltage difference between the bit line pair BL ₁ and ▲ ▼ is From equation (4) "+" Is for H reading, "-" is for L reading. (5)
The first term on the right side of the equation is the read voltage difference due to the original memory cell capacitance Cs, and the second and third terms are adjacent bit line pairs BL ₀ ,
It is the noise component from ▲ ▼, BL ₂ , ▲ ▼ via the coupling capacitance.

[Problems to be Solved by the Invention]

Since the conventional dynamic type semiconductor memory device is configured as described above, as the high integration progresses and the capacitance between adjacent bit lines increases, the read voltage difference decreases due to capacitive coupling noise between the adjacent bit line pairs. However, there are problems that the soft error rate is deteriorated, the read margin is reduced, and the like, which eventually leads to malfunction.

The present invention has been made in order to solve the above problems, and a semiconductor memory device capable of completely reducing a decrease in read voltage amplitude due to noise between adjacent bit line pairs due to a capacitance between the bit lines. Aim to get.

[Means for Solving the Problems]

In the semiconductor memory device according to the present invention, each column of the memory cell array is divided into a plurality of regions by the division regions, the connection bit lines and the passing bit lines are connected in the division regions every other column, and each bit line pair intersects with each other. The intersections are formed only in the portions, and the connection bit lines and the passing bit lines are arranged to extend in the remaining divided regions.

[Operation] In the semiconductor memory device according to the present invention, the intersections are arranged every other column in the divided regions, and the passing bit lines and the connection bit lines extend in the remaining divided regions. It is possible to equalize the capacitive coupling noise received from the adjacent bit lines to all of the bit lines forming the same, and accordingly to eliminate the reduction in the read voltage. Further, the intersecting portions are arranged only in the divided region portions every other row, so that the intersecting portions can be arranged with a margin.

Example of Invention

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be first described.
It will be described with reference to the drawings.

In this embodiment, as shown in the figure, each bit line pair (BL ₀ , ▲
▼, BL ₁ ,…) are divided into four equal parts a, b, c, d, bit line pair BL 0, ▲ ▼ intersect at division points Cp ₁ , Cp ₃ , bit line pair BL 1, ▲ ▼ are Cp Cross at ₂ , bit line pair BL2,
▲ ▼ crosses at Cp ₁ and Cp ₃ , bit line pair BL 3, ▲
▼ intersects at Cp ₂ . The arrangement of the connecting bit line (CB) and the passing bit line (TB) in the bit line pair is as follows for bit line pair BL0, ▲ ▼ and BL2, ▲ ▼.
In section d, each bit line BL0, BL2 is connected bit line (CB),
Each bit line ▲ ▼, ▲ ▼ is a passing bit line (T.
In sections B), b, and c, each bit line BL0, BL2 becomes a passing bit line (TB), each bit line ▲ ▼, ▲ ▼ becomes a connection bit line (CB), and a bit line pair BL ₁ , ▲ ▼ and
In BL ₃ , ▲ ▼, each bit line B in sections a and b
L ₁ and BL ₃ are connection bit (CB), each bit line ▲ ▼,
▲ ▼ is a passing bit (TB), each bit line BL1 and BL3 in sections c and d is a passing bit (TB), each bit line ▲
▼ and ▲ ▼ are connection bit lines (CB).

From this, the capacitive coupling noise received by each bit line pair from the adjacent bit line pair is as follows when considered in the same manner as the above-mentioned conventional example.

Capacitive coupling noise voltage change components ΔVBL1 ′, ΔV ▲ ▼ which the bit lines BL ₁ and ▲ ▼ receive from the adjacent bit lines are And the expressions (6) and (7) are exactly the same.

Capacitive coupling noise voltage change components ΔV BL ₂ and ΔV ▲ received by the bit lines BL ₂ and ▲ ▼ from adjacent bit lines are And the equations (8) and (9) are exactly the same.

Similarly, for all bit line pairs, the bit lines forming each pair receive the same capacitive coupling noise from the adjacent bit line pairs.

As described above, in the present embodiment, since each pair of bit lines receives the same capacitive coupling noise from the adjacent bit line pair at the time of signal reading, the reduction of the read voltage difference due to the capacitive coupling noise is completely eliminated. Can be lost,
It is possible to increase the read margin and improve the soft error rate.

FIG. 2 shows a second embodiment of the present invention. This embodiment is the first
The difference from the embodiment of the figure is that the bit line pair is divided into four sections,
The case where the bit line pair is crossed is shown, but this is divided into eight sections. In this case, considering the same as in the first embodiment, the voltage difference between the bit line and the voltage due to the capacitive coupling noise received from the adjacent bit line can be canceled. In addition, this effect can be similarly obtained even if 12 divisions, 16 divisions ...

〔The invention's effect〕

As described above, according to the present invention, in each bit line pair, the connection bit lines and the passing bit lines are interconnected in the memory cell array division regions so that the bit lines intersect each other, and the remaining bit lines in the remaining division regions are connected. Since the connection bit line and the passing bit line are configured to extend in the portion, the intersection can be arranged with a margin and at the same time all the capacitive coupling noise from the adjacent bit line of each bit line can be blocked, Accordingly, the reduction of the read voltage difference can be prevented, and the operation margin of the sense amplifier can be expanded and the soft error rate can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a structure of a conventional semiconductor memory device. 4 and 5 are block diagrams of a conventional semiconductor memory device. (1) is a column decoder (CD), (2) is a sense amplifier (SA), (3) is a transfer gate Q, (4) is a connection bit line (CB), and (5) is a passing bit line (TB). ),
(6) is the transfer gate T _G , (7) is the memory cell capacity (Cs), (8) is the dummy cell (DC), (9) is the connection bit line capacity (Co), and (10) is the passing bit line. Capacitance (C ₁ ) and (11) are adjacent connection bit line capacity (C ₂ ) and (12)
Is the adjacent passing bit line capacitance (C ₃ ), (13) is the bit line capacitance (C ₄ ), BL ₀ to ▲ ▼ is the bit line, Cp _{1 to} Cp ₃ is the dividing point, and I / 0 ▲ ▼ is the input / output. It is a line. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Arranged in a matrix of rows and columns,
A memory cell array having a plurality of memory cells each for storing information and divided into a plurality of regions in the column direction by a plurality of division regions extending in the row direction; And a plurality of bit line pairs to which the memory cells in the corresponding columns are connected, each of the plurality of bit line pairs being formed of a connection bit line connecting the memory cells and a wiring layer different from the connection bit line. And a bit line which is not connected to the memory cell, and the plurality of bit line pairs are connected bit lines so that the bit lines intersect only at intersections arranged in every other column in each divided region. And the passing bit line are interconnected, and the connecting bit line and the passing bit line are both extended and arranged at the intersections in the divided regions adjacent to each other in the row direction and the column direction. And a plurality of sense amplifiers arranged corresponding to each bit line pair, each sense amplifier for detecting and amplifying a potential difference of the corresponding bit line pair.