JPH0758587B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to prevention of signal read error.

[Conventional technology]

FIG. 4 shows the structure of a bit line pair of a conventional dynamic semiconductor memory device. A plurality of memory cells (Cs) and a transfer gate TG for receiving word line signals (WL ₀ , WL ₁ ...) Are connected to the gates for connecting the memory cells and the bit lines to the bit line pair BL, ▲▲. To be done. In addition, a dummy cell (DC ₀ , DC ₁ ) for generating a reference level and a dummy word line (DWL ₀ , DWL ₁ ) connecting the bit line to the bit cell are connected to each bit line, and the word line and the dummy word line are connected. Rise, and after a signal voltage difference appears on the bit line pair, a sensor amplifier (SA) for sense-amplifying the bit line potential is connected. In addition, the transfer gate Q ₁ for connecting the bit line pair selected according to the column address to the data input / output line pair (I / O, ▲ ▼),
There is ▲ ▼, and the output of the column decoder 1 is input to this gate.

Next, consider the signal voltage appearing on each bit line pair during signal reading.

Each bit line is connected to the ground voltage (fixed potential) C ₁ ,
It has a capacitance of C _{2 for} a pair of bit lines and a capacitance of C ₃ for a bit line of an adjacent bit line pair. The bit line length is 1, and the memory cell capacity is Cs.

For memory cells, “H” level: CsV _CC (V _CC write) “L” level: 0 (0 V write) It is assumed that the electric charge is stored.

When the precharge level of the bit line is V _CC , for example, when a memory cell connected to the bit line BL ₁ is selected and a dummy cell is connected to the bit line ▲ ▼, the potential V _{BL1 of the} bit line BL ₁ , ▲ ▼ , V ▲ ▼ is However, ΔV ▲ ▼, ΔV ▲ ▼, ΔV _BL1 , ΔV
_BL2 is the potential change of the bit line indicated by the subscript.

From the expressions (1) to (3), it is considered that the bit lines BL ₁ and ▲ ▼ have the same precharge level.
From the operations (2) and (1)-(3), the voltage difference between the bit line pair is as follows.

"+" Is for reading "H", "-" is for reading "L". Right side of equation (4), the first term is the original read voltage difference, and the second term is the bit line of the adjacent bit line pair. , BL ₂ is the noise component via the coupling capacitance.

By the way, as the high integration of memory progresses and the bit line pitch decreases, the capacitance C ₃ between the bit line pair increases, and (4)
The second term in the equation becomes larger. Therefore, this causes a problem that the read voltage is remarkably impaired, the read margin is reduced, the soft error rate is deteriorated, and a malfunction finally occurs.

[Problems to be solved by the invention]

Since the conventional dynamic semiconductor recording device is configured as described above, as the degree of integration increases and the capacitance between adjacent bit lines increases, the read voltage difference decreases due to capacitive coupling noise between adjacent bit line pairs. However, there is a problem that the soft error rate is deteriorated, the read margin is reduced, and the like, which eventually causes a malfunction.

The present invention has been made in order to solve the above problems, and a semiconductor memory device capable of completely reducing the decrease in read voltage amplitude due to noise between adjacent bit line pairs due to the capacitance between bit lines to zero. Aim to get.

[Means for Solving the Problems] In the semiconductor memory device according to the present invention, the bit line capacitances between the bit lines forming each pair and the bit line pairs adjacent to each other are all equal. In addition, in order to make the stray capacitances of the entire bit lines of each bit line forming the bit line pair equal to each other, the intersections of the bit lines forming the bit line pair at a plurality of points of the bit line are crossed. It has a structure.

[Action]

According to the present invention, each bit line pair has an appropriate crossing so that the bit line pair makes the capacitive coupling noise received from the adjacent bit line pair completely equal, and the bit line pair bit bit Since the stray capacitances of the entire lines are made equal to each other, it is possible to eliminate the drop in the read voltage difference, and the stray capacitances of the bit lines that make up the bit line pair are balanced, so that the sensitivity of the sense amplifier is improved. Can be improved.

〔Example〕

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be first described.
It will be described with reference to the drawing.

In the present embodiment, as shown in the figure, each bit line pair (BL ₀ , ▲ ▼, BL ₁ , ▲ ▼, ...) Is divided into four equal sections a, b, c, d. Equidistant points of CP ₁ , CP ₂ , CP
_{At 3} , they intersect as follows.

BL ₀ , ▲ ▼ intersects at CP ₂ , BL ₁ , ▲ ▼ intersects at CP ₁ and CP ₃ , ′ BL ₂ , ▲ ▼ intersects at CP ₂ , ′ BL ₃ , ▲ ▼ represents CP ₁ , And CP ₃ , that is, the odd-numbered bit number pairs cross at CP ₂ and the even-numbered bit line pairs at CP ₁ counting from bit line BL ₀ , ▲ ▼.
And cross at CP ₃ . As a result, the capacitive coupling noise received by each bit line pair from the adjacent bit line pair is as follows when considered in the same manner as the above-mentioned conventional example.

Capacitive coupling noise ΔV _BL1 ′, ΔV ▲ ▼ ′ that bit lines BL ₁ and ▲ ▼ receive from an adjacent bit line pair.
Is And both are exactly the same.

The bit line BL ₂ and ▲ ▼ receive capacitive coupling noise ΔV _BL2 ′, V ▲ ▼ ′ from the adjacent bit line pair, And both are exactly the same.

Similarly, for all bit line pairs, the bit lines forming each pair receive the same capacitive coupling noise from the adjacent bit line pairs. For the bit line pair BL ₀ , ▲ ▼ at the end of the memory array, And both are exactly the same.

As described above, in the present embodiment, since the capacitive coupling noise received by the pair of adjacent beat lines at the time of signal reading is equal to each of the paired bit lines, there is no reduction in the read voltage difference due to this noise. You can
It is possible to increase the read margin and improve the soft error rate.

FIG. 2 shows a second embodiment of the present invention. This embodiment is the first
The difference from the illustrated embodiment is that the odd-numbered bit line pairs (BL ₀ ,
▲ ▼, BL ₂ , ▲ ▼ ……), and a crossing is added at the bit line end CP ₄ . It is impossible to lay out the cross points CP ₁ , CP ₂ , CP ₃ provided in the present invention in a completely symmetrical shape with respect to the bit line pair. In the case of the embodiment shown in FIG. ₁ , since there are two intersections in each of the even-numbered bit line pairs (BL ₁ , ▲ ₁ ▲, BL ₃ , ▲ ▼ ...), the bit line pairs as a whole are A balanced layout is possible. For example, the bit line is an Al layer and the wiring layer that can intersect with it is poly-Si.
As for the layer, in CP ₁ , BL ₁ is Al, ▲ ▼ is poly-Si, and in CP ₃ , BL ₁ is poly-Si, ▲ ▼ is Al, which makes the stray capacitance of the bit line pair unbalanced. Can be avoided. In the embodiment of FIG. 2, for the same purpose, a dummy crossing CP ₄ is added so as to balance even the odd-numbered bit line pairs, whereby the capacitance for all the bit line pairs is increased. It is possible to achieve a balanced state.

In the above embodiment, the bit line pair is divided into four sections and intersected at appropriate places, but this section has the same effect even if it is an integral multiple of 8 sections, 12 sections, etc. Play. FIG. 3 shows an embodiment in the case of 8 sections, which is a form in which the form of FIG. 2 is repeated twice, and it is clear that the same effect as the embodiment of FIG. 2 can be obtained. .

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the bit line capacitances of each bit line pair are equal to each other, and the bit line capacitances between adjacent bit line pairs are equal to each other. A structure having crossing portions where the bit lines forming the bit line pair intersect at a plurality of points of the bit line so that the stray capacitances of the entire bit lines forming the bit line pair are equal to each other; As a result, it is possible to prevent the read voltage difference from decreasing, and improve the sensitivity of the sense amplifier by balancing the floating capacitance of the bit line pair, thereby expanding the read margin and improving the soft error rate. There is an effect that can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a third embodiment of the present invention. FIG. 4 is a block diagram showing a semiconductor memory device according to an embodiment, FIG. 4 is a block diagram of a conventional semiconductor memory device, and FIG. 5 is a block diagram of a conventional semiconductor memory device. BL ₀ , ▲ ▼, BL ₁ , ▲ ▼ ， …… bit line, WL ₀ , W
L ₁ , ... word line, C _S ... memory cell, SA ... sense amplifier, CP ₁ , CP ₂ , CP ₃ ... crossing point, CP ₄ ... bit line end,
a, b, c, d ... Classification.

Claims (3)

[Claims] 1. A memory cell array comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells located at intersections thereof, wherein two bit lines are paired to form a pair between the bit line pairs. In a semiconductor memory device having a configuration of inputting to one sense amplifier that detects a voltage difference, each bit line pair has a bit line capacitance between each bit line pair and an adjacent bit line pair. The bit lines forming the bit line pair are crossed at a plurality of positions so that the floating capacitances of all the bit lines forming each bit line pair are equal to each other. A semiconductor memory device having an intersecting portion. 2. Each of the bit line pairs has an even number of intersections, and at half of the even numbered intersections, one bit line forming the bit line pair is the other bit line. Crossing so as to pass through the upper side, and at the remaining half of the crossing portions, the other bit line forming the bit line pair intersects so as to pass over the one bit line. The semiconductor memory device according to claim 1, wherein: 3. When each bit line pair is divided into four equal parts in the lengthwise direction and three equal dividing points and bit line ends are CP ₁ , CP ₂ , CP ₃ , CP ₄ , the bit line pair is A bit line pair having an intersection at an equal point CP ₂ and a bit line end CP ₄ and a bit line pair having an intersection at an equal point CP ₁ and CP ₃ are alternately arranged. 3. The semiconductor memory device according to item 1 or 2.