JPH0766969B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device using a high resistance element formed of a polycrystalline silicon layer as a load and a method for manufacturing the same.

(Prior Art) A memory cell used in a static RAM (random access memory) is generally configured as shown in the circuit diagram of FIG. This memory cell is an inverter using an enhancement type (hereinafter referred to as E type) MOS transistor (insulated gate type field effect transistor) 31 as a driving transistor and a pull-up high resistance element 32 as its load element. This is a so-called E / R type memory cell configured by using two 33. Note that V _CC and V
_SS is a high-potential power supply potential and a low-potential power supply potential of the memory cell, BL and ▲ ▼ are bit line pairs, WL is a word line,
Reference numeral 34 is a transfer gate for selecting a memory cell, each of which is composed of an E-type transistor.

By the way, conventionally, when integrating the above memory cells, MOS
Inverter 33 consisting of transistor 31 and high resistance element 32
Is constructed as shown in the sectional view of FIG. That is, the insulating film 41 is provided on the first conductivity type semiconductor substrate 40, and the polycrystalline silicon layer 42 is deposited on the insulating film 41. Both ends 42A, 42 of the polycrystalline silicon layer 42
Each B is doped with impurities at a sufficient concentration to have a low resistance and serves as a contact region for connecting to the other. However, the intermediate portion 42C is not doped with impurities,
Therefore, this intermediate portion 42C is used as the high resistance element 32.

On the other hand, a pair of diffusion regions 43, 44 doped with impurities of the second conductivity type are formed in the surface region of the substrate 40,
Further, a gate electrode 45 composed of a polycrystalline silicon layer is provided on the substrate between both regions. Both diffusion areas 4
Reference numerals 3 and 44 are the source and drain regions of the MOS transistor 31, and one of the polycrystalline silicon layers is provided in one diffusion region 44, which is the drain region, through a contact hole formed in the insulating film 41. 42A is connected. The other end 42B of the polycrystalline silicon layer is connected to the high-potential-side power supply potential V _CC , and the other diffusion region 43 serving as the source region of the MOS transistor 31 is connected to the low-potential-side power supply potential.
Connected to V _SS .

Thus, both ends 42A and 42B of the polycrystalline silicon layer are usually heavily doped with impurities because it is necessary to make contact with the drain of the MOS transistor 31 and the power supply, respectively. Further, since the high-resistance element is composed of a polycrystalline silicon layer, impurities are diffused abnormally quickly in the subsequent heat treatment, and the intermediate portion 42 where impurities are not doped is formed.
The distance of C becomes short. Therefore, in the past, the third
There is a drawback in that it is difficult to miniaturize the high resistance element 32 in the figure, and thus it is difficult to miniaturize the whole.

Further, conventionally, there is a problem in contact characteristics between the end portion 42A of the polycrystalline silicon layer and the diffusion region 44. In order to obtain a better ohmic contact, it is necessary to dope the polycrystalline silicon layer 42 with a sufficient concentration of impurities.
If the doping amount at this time is too large, punch-through will occur this time.

Further, conventionally, two layers of polycrystalline silicon layers are required for the gate electrode of the MOS transistor 31 and for the high resistance element, so that the manufacturing process is complicated.

(Problems to be Solved by the Invention) As described above, it is difficult to miniaturize a high resistance element when a high resistance element is used as a load in the related art, and further two polycrystalline silicon layers are required. Has the drawback of being complicated.

The present invention has been made in consideration of the above circumstances, and an object thereof is to enable miniaturization of a high resistance element,
Another object of the present invention is to provide a semiconductor device having a relatively simple manufacturing process and a manufacturing method thereof.

[Structure of the Invention] (Means for Solving Problems) A semiconductor device of the present invention is provided with a silicon semiconductor substrate, an element isolation insulating film selectively formed on the substrate, and the insulating film. Not formed on the base body and the insulating film on the periphery thereof and a silicon layer formed continuously from the single crystal silicon layer and the polycrystalline silicon layer, and a part of the single crystal silicon layer of the silicon layer, The source and drain regions of the MOS transistor in which impurities are introduced, and the MO provided on the source and drain regions.
The gate insulating film and the gate electrode of the S-transistor, and the single crystal silicon layer in which the impurities are not introduced are continuously provided in the single crystal silicon layer in which the drain region is set. And a high resistance region formed of a polycrystalline silicon layer.

Further, the method of manufacturing a semiconductor device of the present invention comprises a step of selectively growing an element isolation insulating film on the surface of a silicon semiconductor substrate, and an epitaxial growth method for forming the insulating film on the substrate not provided with the insulating film and on the periphery thereof. A step of continuously growing a silicon layer composed of a single crystal silicon layer and a polycrystalline silicon layer over the insulating film; a step of separating the silicon layer for each element formation planned region; and a step of separating the silicon layer on the separated silicon layer. A step of forming a gate insulating film and a gate electrode, and an impurity is introduced into a part of the single crystal silicon layer of the separated silicon layer to form source and drain regions, and the polycrystalline silicon layer of the silicon layer is formed. Impurities are partially introduced to form a contact region, and impurities are introduced into the silicon layer between the drain region and the contact region. Leaving a polycrystalline silicon layer single crystal silicon layer and the impurity is not introduced is not introduced, characterized by comprising a step of leaving the polysilicon layer the impurity is not introduced as a high resistance region.

(Operation) In the semiconductor device of the present invention, the source and drain regions of the MOS transistor are formed in the single crystal region of the silicon layer formed on the silicon semiconductor substrate, and the high resistance region is formed in the polycrystalline silicon region. Since the contact region of the high resistance region is formed in the single crystal region, and the contact region of the high resistance region is formed in the single crystal region,
Even if impurities are doped, the amount of exudation can be reduced, which makes it possible to strictly determine the size of the high resistance region.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.
1 (a) to 1 (f) are sectional views sequentially showing each step of the method for manufacturing a semiconductor device of the present invention.

First, a field oxide film 11 for element isolation having a film thickness of, for example, about 0.6 μm is formed on the surface of a P-type silicon substrate 10 by selective oxidation by a normal LOCOS method (FIG. 1A).

Next, by CVD (Chemical Vapor Deposition), silicon substrate 1
A silicon layer having a thickness of 0.4 μm is formed on the entire surface under the condition that single crystal silicon is epitaxially grown on the exposed surface of 0. At this time, the crystallinity of the epitaxial layer of the silicon layer 12A formed on the exposed surface of the silicon substrate 10 and in the vicinity thereof is very close to that of the silicon substrate 10. Further, the silicon layer 12B in the portion apart from the exposed surface of the silicon substrate 10 is made of polycrystalline silicon (FIG. 1 (b)).

Next, the silicon layers 12A and 12B are patterned by a selective etching method to selectively leave the silicon layer only in the element formation planned region and remove the other portions (FIG. 1 (c)). The silicon layer left in this process will be MOS in the future.
It will be a region for forming a transistor and a high resistance element.

Next, deposit a silicon oxide film on the entire surface to a film thickness of about 20 nm,
Further, a polycrystalline silicon film is deposited thereon to a film thickness of 0.4 μm, for example, and then both layers are patterned by a lithography technique to form a gate insulating film 13 made of a silicon oxide film.
And a gate electrode 14 made of a polycrystalline silicon film are selectively formed on the silicon layer 12A made of the single crystal silicon (FIG. 1 (d)).

Next, a mask for ion implantation of a predetermined shape by photolithography.
15 is formed, and the mask and the gate electrode 14 are used to remove impurities such as As in the silicon layers 12A and 12B.
Is ion-implanted at a dose of, for example, 40 KeV and 5 × 10 ¹⁵ / cm ² , and thereafter activated. As a result, the N-type source region 16 and the drain region 17 are formed in the single crystal silicon layer 12A, the contact region 18 is formed in the silicon layer 12B made of polycrystalline silicon, and the silicon layer 12B not ion-doped. A high resistance element 19 is formed on the substrate (FIG. 1 (e)). Here, the drain region 17 is formed by implanting ions only in the single crystal silicon layer 12A, and the mask 15 is formed in such a shape that ions are not implanted in the adjacent polycrystalline silicon layer 12B.

Then, after removing the mask 15, an interlayer insulating film 20 such as a BPSG film (boron-phosphorus-silicon glass film) is formed on the entire surface by 1.0.
The interlayer insulating film 20 is deposited with a thickness of μm, contact holes 21 and 22 are formed in the interlayer insulating film 20, and Al is further deposited on the entire surface by a vacuum vapor deposition method.
By forming a wiring 23 for V _SS connected to 16 and a wiring 24 for V _DD connected to the contact region 18, it is composed of a MOS transistor and a high resistance element.
The semiconductor device as an inverter used in M is completed.

According to such a method, conventionally, two layers of polycrystalline silicon layers were required to manufacture an E / R type inverter, but according to the above method, one layer of a polycrystalline silicon layer for a gate electrode of a MOS transistor is used. This can be achieved with a crystalline silicon layer. Therefore, the manufacturing process becomes simpler than the conventional one.

Further, as is clear from FIG. 1 (e), the high resistance region 19
Is partially monocrystallized, and doping of impurity ions for forming the drain region of the MOS transistor is performed on this monocrystallized region, and the silicon layer 12B made of polycrystalline silicon for forming the contact region 18 is formed. Only one end is doped with impurity ions. Therefore, the degree of hindrance to the miniaturization of the high resistance element due to the abnormal diffusion of impurities in the polycrystalline silicon, which was in the prior art, is reduced to about half that of the conventional art, and the miniaturization of the high resistance element 19 can be realized. .

Furthermore, the high resistance element 19 and the drain region 1 of the MOS transistor
Since 7 and 7 can be formed continuously, the problem of contact between the two, which has been a problem in the past, does not occur at all.

FIG. 2 is a sectional view showing an intermediate process according to another embodiment of the present invention. In the above embodiment, the silicon layers 12A and 12B
The case where the selective etching method is used to selectively leave the silicon oxide film only in the element formation planned region has been described. In this case, as shown in FIG. The separation by 25 may be performed. According to the separation method using the silicon oxide film 25 by the selective oxidation as described above, the surface of the substrate is flattened as compared with the method of the embodiment shown in FIG. There is an effect that the occurrence of can be suppressed.

It is needless to say that the present invention is not limited to the above embodiments and various modifications can be made. For example, in the above-described embodiment, an example in which only a part of the silicon layer is epitaxially grown has been described, but this is desirable because if the entire silicon layer is epitaxially grown, the high resistance region has a higher resistance. Also activation energy is 1.1e
Since it is close to V, the leak current also decreases.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor device in which a high-resistance element can be miniaturized and a manufacturing process is relatively simple, and a manufacturing method thereof.

[Brief description of drawings]

1 (a) to 1 (f) are sectional views showing the steps of the method for manufacturing a semiconductor device according to the present invention in sequence, and FIG. 2 is a sectional view showing the steps in the middle according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a general E / R type memory cell, and FIG. 4 is a sectional view showing an element structure of an inverter used in a conventional device. 10 ... P-type silicon substrate, 11 ... Field oxide film, 12A,
12B ... Silicon layer, 13 ... Gate electrode, 14 ... Gate insulating film, 15 ... Mask for ion implantation, 16 ... Source region, 17 ...
Drain region, 18 ... Contact region, 19 ... High resistance element,
20 ... Interlayer insulation film, 21, 22 ... Contact hole, 23 ... Wiring for V _SS , 24 ... Wiring for V _DD , 25 ... Silicon oxide film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 27/11 H01L 27/04 P

Claims (5)

[Claims] 1. A silicon semiconductor substrate, an element isolation insulating film selectively formed on the substrate, and a substrate on which the insulating film is not provided and the insulating film around the substrate are continuously formed. A silicon layer composed of a single crystal silicon layer and a polycrystalline silicon layer, and a source and drain region of a MOS transistor in which impurities are introduced, which is set in a part of the single crystal silicon layer of the silicon layer, and the source, The gate insulating film and the gate electrode of the MOS transistor provided on the drain region, and the single crystal silicon layer in which continuous impurities are not introduced into the single crystal silicon layer in which the drain region is set A high resistance region composed of the polycrystalline silicon layer of the silicon layer into which is not introduced. 2. The MOS transistor and the high resistance region,
The semiconductor device according to claim 1, wherein the semiconductor device is an inverter that constitutes a data storage flip-flop of a static random access memory. 3. A step of selectively growing an element isolation insulating film on the surface of a silicon semiconductor substrate, and a continuous step over the substrate not provided with the insulating film and the insulating film around the substrate by an epitaxial growth method. A step of growing a silicon layer composed of a single crystal silicon layer and a polycrystalline silicon layer, a step of separating the silicon layer for each element formation planned region, and a gate insulating film and a gate electrode on the separated silicon layer. Forming a source and drain regions by introducing impurities into a part of the single crystal silicon layer of the separated silicon layer,
Impurities are introduced into a part of the polycrystalline silicon layer of the silicon layer to form a contact region, and impurities are not introduced into the silicon layer between the drain region and the contact region Single-crystal silicon layer and impurities are not introduced Leaving the polycrystalline silicon layer and leaving the polycrystalline silicon layer into which the impurities are not introduced as a high resistance region. 4. The method according to claim 3, wherein the step of separating the silicon layer is performed by selectively leaving the silicon layer only in each element formation planned region and removing the other regions. Of manufacturing a semiconductor device of. 5. The manufacturing of a semiconductor device according to claim 3, wherein the step of separating the silicon layer is performed by selectively oxidizing a region of the silicon layer other than a region in which each element is to be formed. Method.