JPH076806B2 - Capacity difference-frequency converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) Recently, capacitive sensors have been widely used to detect physical quantities such as pressure, flow rate, and humidity. The present invention relates to signal processing of these capacitive sensors.

(Prior Art) The most common method for measuring unknown capacitance is the AC bridge method. Although this method has high measurement accuracy, it requires an amplifier, a detector, and an analog-to-digital converter in order to extract the result as a digital quantity, which makes the measurement apparatus complicated and expensive. There is an oscillator method that detects capacitance change as frequency change as a simpler method to detect digital quantity with unknown capacitance.Since this method is also suitable for remote measurement, it has attracted attention as a signal processing method for various capacitance type sensors. ing. Conventionally, a multivibrator or a collector tuned oscillator is used as the oscillator.

(Problems to be Solved by the Invention) Generally, the capacitance change of a capacitive sensor is extremely small as compared with its offset (fixed) capacitance. Therefore, high sensitivity cannot be expected in the oscillator system. The present invention was devised to solve this problem, and an object thereof is to provide an oscillator that converts the difference between two capacitors into a frequency.

(Means for Solving the Problem) In order to solve the above-mentioned object, the capacitance difference-frequency converter according to the present invention is such that at least one of the two capacitances (Cx, Cy) that changes according to the physical quantity has a constant voltage for each clock. (CxVc−CyV), which is charged by
A capacitance difference-frequency converter configured to generate a reset pulse when the output of the switched capacitor integrator obtained by accumulating c) is input to the comparator and coincides with the reference voltage. The clock is a two-phase clock including a positive-phase clock that discharges Cx and charges Cy, and a negative-phase clock that charges the capacitor Cx and discharges the capacitor Cy, and the reset pulse is synchronized with the negative-phase clock. The output is the capacitance difference-frequency conversion output, and all the capacitances of the switched capacitor integrator are reset by the reset pulse.

FIG. 1 is a block diagram of a capacitance difference-frequency converter according to the present invention. In the figure, reference numeral 1 is a switched capacitor differential which accumulates a difference between charges charged in two capacitors and outputs a voltage proportional to the accumulated difference. An integrator, 2 is a clock pulse generator for controlling the opening and closing of switches constituting the integrator, and 3 is an integrator 1
Is a reset pulse generator for resetting the integrator 1 every time the comparator 3 inverts its state, and 5 is an input voltage of the integrator 1. Frequency proportional to capacitance difference is terminal 41
Is output from.

(Operation) If the two capacitors are Cx and Cy and the input voltage 5 of the integrator 1 is Vc, the charges charged in the two capacitors are CxVc and CyVc, respectively.
Becomes Since the switched capacitor differential integrator 1 generates a voltage proportional to the difference between both charges in synchronization with the clock pulse from the clock pulse generator 2, the clock frequency fc
The voltage of Vo = K (Cx-Cy) Vc (1) is output in one cycle of. Here, K is a proportional constant. Assuming that this voltage is accumulated n times and the output voltage becomes equal to the voltage Vr of the reference voltage source 6, the cumulative number n is given by the following equation.

At this time, since the comparator 3 inverts the state, the reset pulse generator 4 generates a reset signal and resets the integrator 1. Since the reset signal is generated every n cycles of the clock period from the clock pulse generator 2, the reset signal frequency f is And is proportional to the capacitance difference ΔC = Cx−Cy.

(Embodiment) FIG. 2 shows an embodiment of the present invention in which a switched capacitor integrator 1 includes an operational amplifier 101 and four capacitors Cx, Cy, C.
It is composed of f, Ch, and switches 121 to 129. Φ indicated next to each switch is a two-phase clock pulse that turns on the switch and is output from the clock pulse generator 2. The φ is a positive phase clock pulse and a negative phase clock pulse, respectively. This integrator works as follows. Capacitor Cx at clock
Is connected to the switches 121 and 129 and the capacitor Ch and is charged to the input voltage Vc with the polarity shown. On the other hand, the capacitor Cy is discharged through the switches 124 and 129 and the capacitor Ch at the time of φ clock. Therefore, the electric charge charged in the capacitor Cx at the end of the φ clock is CxVc, and the electric charge in the capacitor Cy is zero. At the next φ clock, the capacitor Cx is discharged through the switch 122, the switch 126 and the capacitor Cf, and the charge CxVc charged in Cx a half clock cycle before is transferred to the capacitor Cf. On the other hand, at the same time as this, the switch 123 and the switch 1 are connected to the capacitor Cy.
The electric charge of CyVc is charged with the polarity shown through 26 and the capacitor Cf. Along with this charging, the same amount of charge is charged in the capacitor Cf with a polarity opposite to that shown in the figure. Therefore, at the time of φ clock, Cf is charged with the electric charge of CxVc having the same polarity as that shown in the figure and the electric charge of CyVc having the opposite polarity to that shown in the figure. Cy) Vc. This net charge increases the voltage across the capacitor Cf by (Cx-Cy) Vc / Cf. Since the voltage between the terminals becomes the integrator output at the time of φ clock, the proportional constant K of the equation (1) becomes 1 / Cf.

The reset pulse generator 4 outputs the reference voltage Vr
Switch 125 and 127 are turned on each time, and the charge accumulated on the capacitor Cf is discharged to reset the integrator 1. The capacitor Ch samples the output of the integrator at the time of φ clock and holds the voltage at the time of clock.

FIG. 3 is an operation waveform diagram for further understanding the above-mentioned operation principle. In this figure, the comparator 3 in FIG. 2 compares the output voltage of the integrator 1 with the reference voltage Vr, and
It is assumed to include a D flip-flop that holds for the clock period. As is clear from the above-mentioned operating principle, the output of the integrator 1 is (Cx−Cy) Vc / C every φ clock.
When it increases by f and this output reaches the reference voltage Vr, a reset pulse is output from the reset pulse generator 4 and the integrator 1 is reset. The number of cycles n of the clock signal φ required from a reset pulse to the next reset pulse is obtained from n (Cx−Cy) Vc / Cf = Vr as shown in equation (2),
As a result, the equation (3) for the reset pulse (output) frequency f is obtained.

FIG. 4 shows Vc = 0.4V, Vr = 1.6 in the embodiment of FIG.
V, Cf = 3.7nF, Ch = 3.3nF, 2-phase clock frequency fc = 100kHz
The relationship between the capacitance difference ΔC = Cx−Cy and the oscillation frequency obtained when This result agrees very well with the theoretical value obtained from the equation (3).

(Effects of the Invention) As described above, according to the present invention, since the capacitance difference can be detected as a frequency change with a simple circuit configuration, the offset capacitance of the capacitive sensor is canceled and the minute capacitance change is detected with high sensitivity. it can. Furthermore, since the circuit configuration can be monolithically integrated, it may be optimal for signal processing of a solid-state capacitance sensor.

[Brief description of drawings]

FIG. 1 is a block diagram of a capacitance difference-frequency converter of the present invention,
2 is a circuit diagram showing an embodiment of the present invention, FIG. 3 is a waveform diagram showing the operating principle of the present invention, and FIG. 4 is a graph showing the relationship between the capacitance difference and the frequency obtained by the circuit of FIG. Is. In FIGS. 1 and 2, 1 is a switched capacitor differential integrator, 2 is a clock pulse generator, 3 is a comparator, 4 is a reset pulse generator, 5 is an input voltage source, and 6 is a reference voltage.

Claims (1)

[Claims] 1. Two capacitances (Cx, Cy), at least one of which changes according to a physical quantity, are charged by a constant voltage (Vc) for each clock, and a difference (CxVc-
CyVc) is accumulated, the output of the switched-capacitor integrator is a capacitance difference-frequency converter configured to generate a reset pulse when the output of the switched capacitor integrator is input to the comparator and coincides with the reference voltage. The clock is a two-phase clock including a positive-phase clock that discharges Cx and charges Cy, and a negative-phase clock that charges the capacitor Cx and discharges the capacitor Cy, and the reset pulse is synchronized with the negative-phase clock. The capacitance difference-frequency conversion output, wherein the capacitance of the switched capacitor integrator is all reset by the reset pulse.