JPH076939B2 - Capacitive sensor signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for processing a signal from a capacitive sensor that detects a physical quantity such as pressure, flow rate, and humidity, and more specifically, it relates to various circuits. The present invention relates to a signal processing circuit which detects a capacitance change of a capacitance type sensor with high sensitivity and outputs it as a digital signal.

(Problems of Prior Art) As a circuit for detecting the capacitance of a capacitive sensor, an astable multivibrator is generally well known.
Although this circuit is simple, the capacitance change of the capacitance type sensor due to the physical quantity to be detected is generally small compared to the offset capacitance, so that highly sensitive detection cannot be expected. There is an AC bridge that is well known as a method of canceling the offset capacitance and detecting only the capacitance change. This AC bridge can detect minute changes in capacitance, but this method uses an AC voltage source, a high-gain differential amplifier, a detector, and an analog signal if the detection result is to be taken out as a digital signal.
Since a digital converter is required, the signal processing circuit becomes complicated and it is difficult to integrate it with the capacitive sensor.

The present invention has been made to solve these problems and provide an inexpensive signal processing circuit that can be integrated with a capacitive sensor.

(Means for Solving Problems) FIG. 1 is a block diagram of a signal processing circuit of a capacitive sensor according to the present invention, in which 1 is a capacitive sensor, 2 is a first reference capacitor, and 3 is a second reference capacitor. The reference capacitor, 4 is a clock generator that controls the operation timing of the signal processing circuit, and 5 is the charge charged in the capacitive sensor 1 for each clock and the first
, An integrator that integrates the difference between the electric charge charged in the reference capacitor, 6 is a comparator that determines the polarity of the output voltage of the integrator, and 7 is an integrator 5 each time the output polarity of the comparator is inverted.
The switch control circuit that controls the opening and closing of the switches 32 and 33 so as to extract the electric charge charged in the second reference capacitor 3 from the electric charge integrated in the. Coefficient over time,
This is a counter that outputs a digital signal proportional to the capacitance change of the capacitive sensor. In this block diagram and the following embodiments, the clock signal φi (i = 1,2,3,4,5) shown next to each switch is a digital signal for controlling the opening / closing of the switch, and this signal is a positive logic signal. It is assumed that the switch is closed during the level 1 level.

(Operation) The operation of the signal processing circuit of the capacitive sensor of the present invention will be described in detail with reference to the embodiment shown in FIG. In FIG. 2, the capacitance of the capacitive sensor 1, the capacitance of the first reference capacitor 2, and the capacitance of the second reference capacitor 3 are Cx, Cc, and Cr, respectively.
The voltages of the third voltage source are Va, Vb, and Vc, respectively. The clock generator 4 is composed of a resistor 43, a capacitor 44, inverters 41, 42, 43 and NOR gates 46, 47, and outputs two-phase clock signals φ ₁ and φ ₂ . Since the capacitive sensor 1 is connected to the first voltage source 11 via the switch 12 at the clock φ ₁ , the electric charge CxVa is charged in the capacitance of the capacitive sensor. On the other hand, since one terminal of the first reference capacitor 2 is connected to the second voltage source 21 via the switch 22 and the other end is connected to the virtual ground terminal 58 of the operational amplifier 51, the first reference capacitor 2 is connected. 2 is charged with an electric charge of CcVb. The integrator 5 includes an operational amplifier 51 and a capacitor 56.
57, and a switched capacitor integrator composed of switches 52 to 55, which holds the integrator output charged in the capacitor 57 at the last φ ₂ clock at the φ ₁ clock. Assuming that the voltage polarity is positive, the Q output of the comparator 6 including the comparator 61 and the D flip-flop 62 has a logic level 0 and the output has a logic level 1.

Therefore, the φ ₄ output of the switch control circuit 7 composed of the AND gate 71 and the OR gate 72 is a logical 0, and the φ ₅ output is a logical 1
In this state, the second reference capacitor 3 is grounded via the switch 33. Further, the counter 8 does not perform the counting operation even though the φ ₁ clock signal is input to the clock terminal 81 because the logic level of the counting enable (CE) input terminal 82 is 0.

At the next φ ₂ clock, the capacitive sensor 1 and the first reference capacitor 2 are charged CxV because the switches 52, 23 and 53 are closed.
Transfer a and CcVb to capacitor 56. At this time, since the polarities of the transferred charges are opposite to each other, the net electric charge charged in the capacitor 56 is CxVa−CcVb, so that the output voltage of the integrator 5 is (CxVa−CcVb) / C ₁ only. Decrease. The integrator output voltage polarity at this time is determined by the comparator 6,
If the polarity is positive, the one cycle operation is repeated until the integrator output voltage becomes negative. On the other hand, when the output voltage polarity of the integrator 5 is negative, the Q output of the comparator 6 is logic 1,
Since the output is in the logic 0 state, the counter 8 increments in the next φ ₁ clock, and at the same time, the φ ₄ output of the switch control circuit 7 becomes the logic 1 and the switch 32 is closed, and the second reference capacitor is connected. Charge CrVc. This charge is transferred to the capacitor 56 together with the charges CxVa and CcVb at the next φ ₂ clock. The net charge transferred is CxVa
In -CcVb-CrVc, CrVc + CcVb> output voltage of the integrator 5 if you choose CrVC so that CxVa is positive, the value is Hoho (CrVc + CcVb + CxVa) / C 1.

Now, the circuit of FIG. 2 repeats the above charge integration operation for 2n cycles of the two-phase clock signals (φ ₁ , φ ₂ ), of which the Q output of the comparator 6 becomes the logic 1 state only m times. If so, the total amount of electric charge sent from the capacitive sensor 1 to the integrator 5 is 2nCxVa, and the total amount of electric charge from the first reference capacitor 2 to the integrator 5 is
Is 2nCcVb, and the total amount of charges sent from the second reference capacitor 3 to the integrator 5 is mCrVc.
Considering the above-mentioned charge polarities, the following inequality holds.

2n (CxVa−CcVb) −mCrVc ≦ CrVe (1) The formula (1) is modified to obtain the following formula.

If the offset capacitance of the capacitive sensor 1 is C ₀ and the capacitance change due to the physical quantity to be detected is ΔC, then Cx = C ₀ + ΔC. Now, the first reference capacitor 2 or the first reference capacitor 2 or the first voltage source 21 is set so that CoVa = CcVb, an n-bit binary counter is used as the counter 8, and m _{1 is set} to The most significant digit, mn, is the least significant digit (LS
Assuming B), equation (2) is within the error range of 1LSB. Becomes Expression (3) shows that the capacitance change of the capacitive sensor is detected as a digital signal by the signal processing circuit of the present invention.

(Effects of the Invention) As described above, according to the present invention, it is possible to detect a capacitance change of a capacitance type sensor with a simple circuit configuration and take it out as a digital signal. Further, the circuits shown in the embodiments can be easily integrated with the current CMOS technology, and thus can be integrated with the capacitive sensor. Therefore, the present invention is extremely useful as a signal processing circuit for making a capacitive sensor intelligent.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal processing circuit of a capacitive sensor of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 and 2, 1 is a capacitive sensor, 2 is a first
Reference capacitor, 3 is a second reference capacitor, 4 is a clock generator, 5 is an integrator, 6 is a comparator, 7 is a switch control circuit, and 8 is a counter.

Claims (1)

[Claims] 1. A capacitive sensor (1) connected to a first voltage source via a switch and a first reference capacitor (2) connected to a second voltage source via another switch. ), A second reference capacitor (3) connected to a third voltage source via a further switch, and a clock generator (4) for generating a clock signal for controlling the opening and closing of the switch. An integrator (5) for integrating the difference between the charge charged in the capacitive sensor and the charge charged in the first reference capacitor for each cycle of the clock signal from the clock generator; And a comparator (6) for determining the output voltage polarity of the second comparator so that the charge accumulated in the second reference capacitor is extracted from the charge accumulated in the integrator each time the output of the comparator is inverted. Connected to the reference capacitor of 2 A switch control circuit (7) for controlling the opening and closing of the switch, and a count for counting the number of times the output of the comparator is inverted over a predetermined period and outputting a digital signal proportional to the capacitance of the capacitance type sensor. And a signal processing circuit of a capacitive sensor including a container (8).