JPH0769836B2 - Microprocessor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a microprocessor, and more particularly to a microprocessor having a small time base error of a signal output through an output port.

2. Description of the Related Art In recent years, Neumann microprocessors have been widely used in all fields, and their configurations include a program storage means for storing a program consisting of a series of instructions to be sequentially executed and a data storage for reading / writing digital data. Means, an arithmetic means for executing arithmetic operation of digital data, a data bus connecting the input / output terminal of the data storage means and the input / output terminal of the arithmetic means, and the above-mentioned means based on an instruction sent from the program storage means. Control means for controlling the operations of the data storage means and the arithmetic means, a timing generator for generating an instruction execution timing signal, and a specific instruction stored in the program storage means based on the output of the timing generator. Characterized by having instruction selection means Be done. In addition, the representative structure is Japanese Patent Publication Sho 58-33584.
Japanese Patent Publication (hereinafter, referred to as Document 1).

SUMMARY OF THE INVENTION However, since the Neumann method microprocessor as shown in the above-mentioned Document 1 executes data processing in a predetermined order, it asynchronously operates as the program becomes huge. The cycle of capturing the input external data and processing of the data based on it becomes long, and as a result, the time variation from the occurrence of the event to the output signal from the microprocessor, that is, the time base error is It has the problem of becoming quite large. For such problems,
In the past, a means called interrupt was used, but even if there is an interrupt request, it cannot move to interrupt processing unless the instruction being executed at that time is processed, so after the microprocessor accepts the interrupt, In addition, there is a problem that a time base error occurs in the time itself until the interrupt service routine is started.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a microprocessor having an output port capable of outputting a series of signal patterns with a small time base error.

Means for Solving the Problems To achieve this object, a microprocessor of the present invention includes a free-running counter that performs a cyclic count operation based on a specific clock signal, and comparison data that stores at least two types of digital data. Any one of a storage unit, a master latch unit that stores the same number of digital data as the comparison data storage unit, a comparison data selection unit that selects one of the comparison data storage units, and the master latch unit. Master latch section selecting means, a cyclic selection command means for outputting a cyclically changing selection signal, and a cyclic stopping means for stopping cyclically changing the selection signal output from the cyclic selection command means. And count data of the free running counter and data of the comparison data storage means And comparing means for outputting a coincidence signal when they coincide with each other, and an output port comprising a slave latch portion for taking in the digital data of the master latch portion based on the coincidence signal of the comparing means.

Effect of the Invention The present invention can obtain a microprocessor having a small time base error of a signal output through the output port, with the above configuration.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the microprocessor of the present invention. In FIG. 1, TMGR100 is a timing generator that generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and its output signal is supplied to the PC200, ICR900 and FRC1000. The PLA300 is a programmable logic array, and stores a program including a group of instructions that are sequentially executed. PC200 is a program counter, TMG
Select a specific instruction stored in PLA300 based on the output signal of R100. FRC1000 is a free-running counter, which performs a cyclic counting operation using the output signal of TMGR100 as a clock signal. The ICR900 is an input capture register circuit, and when the edge of the input signal applied to the external signal input terminals 30 to 37 arrives, the FRC100 at that point in time.
The count data of 0 is stored in a specific register in the ICR900 (when the edges of a plurality of input signals arrive at the same time, the count data of the FRC1000 is stored in a plurality of registers), and an input signal acceptance flag (not shown) is set. It has the function of setting. The command sent from the PLA 300 is ALU 400, address decoder 600 (shown as address decoder A in the figure), and address decoder 800 (shown as address decoder B in the figure) via the control bus 1300. ), ICR900 and output port 110
Supplied to 0. Data bus 1200 is ALU400, ROM50
0, RAM700, ICR900 and output port 1100. ALU400 is an arithmetic unit that executes arithmetic and logical operations on digital data. The ROM 500 is a read-only memory that sends digital data stored in advance to the data bus 1200. The RAM 700 is a random access memory that reads and writes digital data via the data bus 1200. The output port 1100 outputs a series of signal patterns that can be changed by a program from the signal output terminals 40 to 47. The address decoder 600 selects the address of the ROM 500, and the address decoder 800 selects the address of the RAM 700.

The operation of the microprocessor of this embodiment configured as described above will be described below with reference to FIGS. 1, 2, and 3.

The TMGR100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and supplies this signal to the PC200, ICR900 and FRC1000. PC200
Selects a specific instruction from the instruction group stored in PLA300 based on the output signal of TMGR100, and
Send to. The ALU400 executes arithmetic and logical operations on digital data sent via the data bus 1200 in accordance with instructions sent from the command bus 1300,
The result is sent to the data bus 1200. The address decoder 600 selects a specific address based on an instruction sent via the command bus 1300, and the ROM 500 transfers the digital data stored in the storage means corresponding to the address selected by the address decoder 600 to the data bus 1200. Send to. The address decoder 800 selects a specific address on the basis of an instruction sent via the command bus 1300, and the RAM 700 sets the data bus 1200 to the storage means corresponding to the address selected by the address decoder 800.
The digital data sent from is stored or the already stored digital data is sent to the data bus 1200.

Next, the output port 1100 will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing the internal structure of the output port 1100 of FIG. 1, and FIG. 3 is a timing chart of the main part.

In FIG. 2, comparison data registers 1111-1114 (shown as comparison data registers A, B, C, D in the drawing) store digital data for comparison with the count data of FRC1000 in FIG. The comparison data selection circuit 1120 selects any one of the comparison data registers 1111-1114 and supplies the digital data stored in the selected register to the comparison circuit 1130. The comparison circuit 1130 receives the digital data supplied from the comparison data selection circuit 1120 and the FRC 100 of FIG.
The count data supplied from 0 is compared, and if they match, a match signal is supplied to the slave latch circuit 1160 and the AND gate 1175. Further, the address decoder 1110 (indicated as an address decoder C in the figure) follows a command sent from the command bus 1300,
An address is selected when digital data is stored in the comparison data registers 1111-1114 via 1200. Master latches 1141 to 1144 (indicated as master latches A, B, C, D in the figure) are latches for storing data to be output, and master latch selection circuit 1150 is a master latch 11
Any one of the master latches 41 to 1144 is selected, and the digital data stored in the selected master latch is supplied to the slave latch circuit 1160. Further, the address decoder 1140 (indicated as an address decoder D in the figure) follows the instruction sent from the command bus 1300 and, in response to the instruction sent from the command bus 1300, the master latch 1141 via the data bus 1200.
Select an address when storing digital data in ~ 1144. The selection signal generation circuit 1180 has four selection signals 1181 to
1184 is supplied to the comparison data selection circuit 1120 and the master latch selection circuit 1150, and one of the four selection signals is sequentially enabled based on the output signal of the AND gate 1175. The patrol stop instruction circuit 1170 is the command bus 1300.
"0" or "1" is stored according to the instruction sent from the output from the OR gate 1174.
Further, the other input terminal of the OR gate 1174 is supplied with one output terminal of the flip-flop constituted by the NOR gate 1172 and the NOR gate 1173. NOR gate 117
The selection signal 1184 is connected to one input terminal of the flip-flop constituted by 2,1173, and the output of the one-cycle detection reset circuit 1171 is connected to the other input terminal.

The operation of the output port 1100 configured as above will be described.

Arbitrary digital data is written in the comparison data registers 1111-1114 by a program. For example, when the comparison data is written in the comparison data register 1111 by the program, first, according to the instruction sent via the command bus 1300, the address decoder 1110
Selects the comparison data register 1111, and the selected comparison data register 1111 stores the digital data sent via the data bus 1200. Similarly, arbitrary digital data is written in the comparison data registers 1112 to 1114. Further, in the master latches 1141 to 1144, arbitrary digital data is similarly written by the program.

Comparison data selection circuit 1120 and master latch selection circuit 11
Reference numeral 50 selects the comparison data register and the master latch corresponding to the four selection signals supplied from the selection signal generation circuit 1180, respectively. The comparison data selection circuit 1120 uses the comparison data register 11 when the selection signal 1181 is enabled.
11, the comparison data register 1112 when the selection signal 1182 is enabled, the comparison data register 1113 when the selection signal 1183 is enabled, the comparison data register 1114 when the selection signal 1184 is enabled, and the master latch is selected. The circuit 1150 includes a master latch 1141 when the selection signal 1181 is enabled, a master latch 1142 when the selection signal 1182 is enabled, a master latch 1143 when the selection signal 1183 is enabled, and a selection signal 1184 when the selection signal 1184 is enabled. To select the master latch 1144.

Next, the operation of outputting a series of output patterns will be described with reference to FIG. FIG. 3a shows the time change of the count data of FRC1000, and FIG.
And d are the coincidence signals of the comparison circuit 1130,
FIGS. 3C and 3E show changes in the latch data of the slave latch circuit 1160. That is, the FRC1000 is a down counter, and the comparison data registers 1111-1114 store comparison data N _A , N _B , N _C , N _D (N _A > N _B > N _C > N _D ), Output data to master latches 1141 to 1144 respectively
Assuming that D _A , D _B D _C , and D _D are stored, the selection signal generation circuit 1180 enables the selection signal 1181 in the initial state, so that the comparison data selection means 1120 causes the comparison data register 1111 to operate. The master latch selection circuit 1150 selects the master latch 1141 and sends the digital data N _A stored in this register to the comparison circuit 1130.
The digital data D _A stored in this latch is sent to the slave latch circuit 1160. The comparison circuit 1130 compares the digital data N _A stored in the comparison data register 1111 with the count data of the FRC1000 shown in FIG. 1 sent via the local bus 1190, and at time t1, F
When the count data of RC1000 becomes N _A , the match signal shown in FIG.
Send to 175. The slave latch circuit 1160 latches the digital data D _A stored in the master latch 1141 by the coincidence signal sent from the comparison circuit 1130 as shown in FIG. 3c. AND gate 1175 is OR gate 1
When the output of 174 is "1", the coincidence signal transmitted from the comparison circuit 1130 is transmitted to the selection signal generation circuit 1180. The selection signal generation circuit 1180 switches the selection signal in the enabled state from 1181 to 1182 by the coincidence signal sent from the comparison circuit 1130. When the selection signal 1182 is enabled, the comparison data selection circuit 1120 changes the comparison data register 1112.
The digital data N _B stored in the master latch 1142 is sent to the comparison circuit 1130.
Digital data stored in D _B Slave latch circuit 11
Send to 60. The comparison circuit 1130 is a comparison data register 1112.
The digital data N _B stored in the FRC1000 is compared with the count data of the FRC1000 sent via the local bus 1190. When the count data of the FRC1000 becomes N _B at time t2, the match signal shown in FIG. It is sent to the slave latch circuit 1160 and the AND gate 1175. Slave latch circuit 1160
Holds the previously latched output data D _A until the match signal is sent from the comparison circuit 1130.
Upon receipt of the coincidence signal sent from the device, the digital data D _B stored in the master latch 1142 is latched as shown in FIG. 3c. Also, the selection signal generation circuit 1180 switches the selection signal in the enabled state from 1182 to 1183 by the coincidence signal sent from the comparison circuit 1130 as described above.

After that, similarly, at times t3 and t4, the local bus 1190
Since the count data of the FRC1000 sent via the match with the comparison data sent from the comparison data selection circuit 1120, a match signal is sent from the comparison circuit 1130, and the slave latch circuit 1160 is selected by the master latch selection circuit. The digital data stored in the master latch is latched, and the selection signal generation circuit 1180 selects the selection signals 1183 and 1184.
Are sequentially switched to the enabled state. Then, every time the selection signal in the enabled state is switched, the comparison data selection circuit 1120 sends the comparison data and the master latch selection circuit 1150 to the comparison circuit 1130 and the slave latch circuit 1160.
The digital data to be sent to is switched. Therefore, with respect to the count data of the FRC1000 of FIG. 1 at a certain time, the data after arbitrary counting is stored in the comparison data registers 1111-1114, and the comparison data registers 1111-1114 are stored.
By storing arbitrary data in the master latches 1141 to 1144 corresponding to, a signal having a series of output patterns can be output from the slave latch circuit.

The flip-flop formed by the NOR gates 1172 and 1173 is NOR gate 117 when the selection signal 1184 is enabled.
The output of 2 is inverted from “1” to “0”, and the selection signal generation circuit 118
It is detected that 0 switches all the selection signals 1181 to 1184 to the enable state. That is, NOR gates 1172, 11
The flip-flop constituted by 73 is a one-cycle detection circuit, and when detecting one cycle, sets the signal supplied to the OR gate 1174 to “0”. At this time, the patrol stop instruction circuit 1170
When the output of is 0, the output of the OR gate 1174 is 0 and the output of the AND gate 1175 is fixed at 0, so the match signal output from the comparison circuit 1130 is the selection signal. It is no longer supplied to the generation circuit 1180. Therefore, when the output of the patrol stop instruction circuit 1170 is “0”, the comparison register 11
According to the digital data stored in 11 to 1114 and master latches 1141 to 1144, the signal pattern output from the slave latch is output only once as shown in FIG. 3c.

If the output of the patrol stop instruction circuit 1170 is "1", OR
NOR gate 1 because the output of gate 1174 is fixed at “1”
The match signal output from the comparison circuit 1130 regardless of the output state of the flip-flop configured by the 172 and the NOR gate 1173 passes through the AND gate 1175 and the selection signal generation circuit 1180.
Will continue to be supplied to. Therefore, the patrol stop instruction circuit 1170
When the output of "1" is "1", the signal pattern output from the slave latch according to the digital data stored in the comparison registers 1111-1114 and master latches 1141-1144 is continuously output as shown in FIG. 3e. Will be done.

The output of the loop detection circuit composed of NOR gates 1172 and 1173 can be set to "1" by the signal output from the loop detection reset circuit by an instruction sent from the command bus 1300. The output of the stop instruction circuit 1170 can also be set in an arbitrary state by an instruction sent from the command bus 1300. Therefore, it is possible to output an arbitrary signal pattern one-shot or continuously.

As described above, the data transfer from the master latches 1141 to 1144 to the slave latch circuit 1160 is performed by the comparison data register 11
11 to 1114 is compared with the count data of FRC1000, and is configured to be automatically performed by the match detection signal of the comparison circuit 1130, thereby detecting the edge of the external signal that is asynchronously input and then determined in advance. When a signal having an arbitrary signal pattern is transmitted from the output port 1100 after the elapse of time, the time base error can be suppressed to the minimum.

As described above, according to the present invention, the free-running counter (1000) that performs the cyclic counting operation based on the specific clock signal and the comparison data storage means (comparison data register 11) that stores at least two types of digital data are provided.
11 to 1114), a master latch unit (master latches 1141 to 1144) that stores the same number of digital data as the comparison data storage unit, and a comparison data selection unit (comparison unit) that selects one of the comparison data storage units. A data selection circuit 1120), a master latch section selection means (master latch selection circuit 1150) for selecting one of the master latch sections, and a cyclic selection command means (selection signal) for outputting a selection signal to be cyclically changed. The generation circuit 1180) and the cyclic stop means (the cyclic stop instruction circuit 11) for stopping the cyclic change of the selection signal output from the cyclic selection command means.
70, NOR gates 1172, 1173, OR gate 1174) and a comparison means (comparison circuit 1130) for comparing the count data of the free running counter with the data of the comparison data storage means and outputting a coincidence signal when they coincide. And an output port 1100 comprising a slave latch unit (slave latch circuit 1160) for taking in the digital data of the master latch unit based on the coincidence signal of the comparing means.

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily obtain a series of signal pattern outputs with less time base error.

In the embodiment, the comparison data register and the master latch of the output port are each configured with four, but even if two or more are provided depending on the complexity of the pattern of the signal output from the output port, it is completely impossible. Similar effects are obtained.

As described above, according to the present invention, when the edge of the input signal applied to any of the external signal input terminals arrives, the input capture register immediately outputs the count data of the free running counter as timing information at that time. Since it is stored in a specific register in the input capture register, the exact arrival time of the input signal can be confirmed by software, and the output port having a series of signal patterns can output the output signal up to the target time. If the time difference data is sent to the data bus and stored in the comparison data register, and the data stored in the comparison data register that is to be output at each set time is stored in the master latch via the data bus, the time base is output from the output port. A series of signal patterns with few errors can be output. It is possible to obtain a microprocessor capable of achieving high efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram showing a concrete configuration example of an output port section, and FIG. 3 is a timing chart of the main part of FIG. . 100 ... Timing generator, 200 ... Program counter, 300 ... PLA, 400 ... ALU, 500 ... ROM, 700 ...
RAM, 900 ... ICR, 1000 ... FRC, 1100 ... output port, 1111-1114 ... comparison data register, 1141-1144 ...
… Master latch, 1160… Slave latch.

Claims (4)

[Claims] 1. A free-running counter for performing a cyclic counting operation based on a specific clock signal, a comparison data storage means for storing at least two kinds of digital data, and the same number of digital data as the comparison data storage means. Master latch unit, a comparison data selection unit that selects any one of the comparison data storage units, a master latch selection unit that selects any one of the master latch units, and a cyclically changing selection A cyclic selection command means for outputting a signal, a cyclic stop means for stopping the cyclic change of the selection signal output from the cyclic selection command means, count data of the free running counter and the comparison data selection means. The data in the selected comparison data storage means is compared, and if they match, the A microprocessor comprising: a comparison unit that outputs a match signal; and an output port that is a slave latch unit that takes in digital data of the master latch unit based on a match signal of the comparison unit. 2. The microprocessor according to claim 1, further comprising comparison data selecting means and master latch section selecting means for changing the selection based on a selection signal output from the cyclic selection command means. 3. A cyclic selection command means for changing the selection signal according to the coincidence signal output from the comparison means.
The described microprocessor. 4. When the patrol stop means indicates the patrol stop state, when the comparison data selection means finishes selecting all the data in the comparison data storage means, the change of the selection signal is stopped, and the patrol stop means changes the patrol state. 2. The microprocessor according to claim 1, further comprising cyclic selection commanding means for cyclically changing the selection signal each time the coincidence signal of the comparing means is output.