JPH0769860B2 - Cache memory store method - Google Patents

Description

The present invention relates to a cache memory control device, and more particularly to a store system for writing data from a store buffer to a cache memory.

[Conventional technology]

Conventionally, in a cache memory control device having this type of store buffer, when writing data from the store buffer to the cache memory, a process of reading the data issued to the main storage device before this writing (hereinafter referred to as block load; , Block is a unit of copy of cache memory and main memory, and here it is 64 bytes. Wait until the end, and after the block load data is written in the cache memory, the above write processing (store processing) is executed. Has been done. That is, the store processing is performed after the block load data is written in the cache memory in order to prevent the block load data from being rewritten incorrectly due to the preceding store processing.

[Problems to be solved by the invention]

By the way, in the case of the conventional store method described above, writing from the store buffer to the cache memory is always suppressed while the block load is being performed to the main memory. Therefore, the free time of the cache memory (the cache memory is not used because the subsequent read access is waited during the block load) cannot be used for the store process, and therefore the subsequent read access is stopped and the cache memory is used. There may be a situation that must be done, and as a result, there is a problem that the system performance is reduced.

[Means for solving problems]

According to the present invention, a bypass buffer that temporarily holds data read from a main storage device, a bypass buffer address register that holds a main storage address of data held in the bypass buffer, and a read address of the bypass buffer address register And an address match detection circuit for detecting a match between the read address of the store address buffer and a read address of the store address buffer, and control means for rewriting the corresponding area of the bypass buffer with the data of the store data buffer based on the output of the address match circuit. It has a feature.

〔Example〕

 The present invention will be described below with reference to examples.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, the request register 1 is a register that holds address information composed of a request code part including an access request type and instruction content, and an access request address part.

The request code part is input to the main memory access control circuit 2 by the connection 50, while the address part is an address array.
Stored in 14. The main memory access control circuit 2 decodes this request code section and is controlled by the address section from the address array 14, and generates and distributes necessary control signals to each section. Further, the address information is input to the switching circuit 3 through the connection 51 and becomes a main memory request address as described later. Further, the address information is input to the store address buffer 4 and the bypass buffer address register 5 via the connections 53 and 54, respectively, and the store address buffer 4 and the bypass buffer address register 5 hold the address at the time of storing and the address of the bypass buffer 6, respectively. .

The store data at the time of store request is input to the store data buffer 7 by the connection 55, and from the connection 56 to the main memory,
Connection from connection 57 to data array 9 through switching circuit 8
Input from 58 to the bypass buffer 6 through the switching circuit 10.

The main memory read data is stored in the bypass buffer 6 from the connection line 59 through the switching circuit 10, while the data return to the request source is performed from the connection line 60 or 61 through the switching circuit 11.

When writing the contents (data) of the store data buffer 7 to the data array 9, the contents (address) of the store address buffer 4 corresponding to the contents of the store buffer data 7 are read out and sent to the comparison circuit 12 by the connection 62. On the other hand, the bypass buffer address register 5 in which the address of the data held in the bypass buffer 6 is stored
Is sent to the comparison circuit 12, and the contents of the store address buffer 4 and the contents of the bypass buffer address register 5 are compared by the comparison circuit 12.

When the contents of the store address buffer 4 and the contents of the bypass buffer address register 5 match, that is, when the block addresses match, the matching result is notified to the bypass buffer control circuit 13. Then, at the same time as writing the data from the store data buffer 7 to the data array 9, the connection 58 instructs the writing to the corresponding area of the bypass buffer 6 via the switching circuit 10.

In the above-described embodiment, when the comparison circuit 12 detects that the addresses match, writing from the store data buffer 7 to the data array 9 is continued without being suppressed, but this is applicable only to the bypass buffer 6. This is because there is data to be written, so there is no problem even if writing is suppressed.

〔The invention's effect〕

As described above, in the present invention, the detection circuit for detecting the match between the store address and the bypass buffer address is provided, and when the detection circuit detects the address match, the store process is performed on the bypass buffer. Therefore, there is an effect that it is possible to improve the performance deterioration of the store processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1,5 …… Register, 2,13 …… Control circuit, 3,8,10,11,12 ……
Switching circuit, 4 …… Store buffer, 6 …… Bypass buffer, 7 …… Store data buffer, 9 …… Data array, 14
...... Address array.

Claims (1)

[Claims] 1. An address array for storing a copy of an address of a main memory, a data array for storing a copy of the data of the main memory, and a store address temporarily storing an update target address of the address array. In a cache memory control device having a store address buffer for storing and a store data buffer for temporarily storing store data which is update data of the data array, a bypass buffer for temporarily holding data read from the main storage device. And a bypass buffer address register for holding a main storage address of data held in the bypass buffer, and an address match detection circuit for detecting a match between a read address of the bypass buffer address register and a read address of the store address buffer. And the address The coincidence detection circuit output, the cache memory store method, characterized by comprising a writing changing control means to the appropriate area of the bypass buffer data of the store data buffers.