JPH0770166B2 - Bit synchronization circuit - Google Patents

Description

The present invention relates to a digital signal reproducing apparatus, and more particularly to a bit synchronizing circuit suitable for fast-forward rewinding reproduction in a rotary head type magnetic recording / reproducing apparatus.

[Prior Art] In a conventional bit synchronization circuit, a phase locked loop (PLL circuit) is designed so that an error rate is improved in normal reproduction, and this is mentioned in JP-A-59-124013. Circuit is used.

[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into consideration that the data transmission rate fluctuates significantly at the time of high-speed search particularly in the rotary head type magnetic recording / reproducing apparatus. At this time, there is a drawback that the data cannot be reproduced.

It is an object of the present invention to reproduce data without performance degradation during normal reproduction even when the transmission rate fluctuates significantly compared to normal reproduction during high-speed search.

[Means for Solving Problems] The above object is achieved by providing means for switching the constant of the loop filter of the PLL circuit to the high frequency side.

[Operation] Since the loop filter is selected on the low frequency side during normal playback, it is possible to suppress the occurrence of jitter due to pulse-like internal disturbances of the phase comparator, etc., and it is possible to eliminate data errors. From choosing to
The capture range is large, and data can be captured by following large fluctuations in the transmission rate.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. First
The figure shows the configuration of a rotary head type magnetic recording / reproducing apparatus according to the present invention. 1 in FIG. 1 is a cylinder,
Two heads 2A and 2B having different azimuth angles are attached, and data is recorded / reproduced on / from the tape 3 when the cylinder 1 rotates. The reel 4 on the feed side, the reel 5 on the take-up side, and not shown. The tape 3 is sent by a capstan. The signals from the heads 2A and 2B are coupled to the switch 12 via a rotary transformer (not shown). In the recording process, the analog signals added to 6L and 6R are analog processed by the audio circuit 7 such as the presence or absence of emphasis, and sampled at a constant sampling frequency in S / H8L and 8R. It is converted into digital data by the D converter 9. In the recording signal processing circuit 10, this PC
Recording amplifier 11 which receives M audio data and control signals such as song number, time, and song start signal from the microcomputer 21 and performs error correction code addition and synchronization signal addition according to a fixed format Join the switch via. At the time of recording, the switch 12 selects the recording amplifier 11 side, applies a signal to the heads 2A and 2B, and records the signal on the tape 3.

During playback, switch the signal played by heads 2A and 2B
It is added to the reproduction amplifier 13 via 12 and amplified to perform waveform equalization processing. After that, the waveform shaping circuit 14 shapes the pulse waveform to 1 and 0 and adds the pulse waveform to the bit synchronization circuit 15. The output data and the clock of the bit synchronization circuit are added to the reproduction processing circuit 16 to detect and correct the data error of the PCM audio data and the control signal, and the audio data is processed by the D / A converter 1.
To 7, the control signal is applied to the microcomputer 21. The output of the D / A converter 17 outputs an analog signal to 20L and 20R via the S / H circuits 18L and 18R and the audio circuit 19.

In such a configuration, the bit synchronization circuit 15 performs the operation of fetching data in the flip-flop 100,
The clock is generated by the PLL circuit composed of the data of the waveform shaping circuit 14 and the clock of the voltage controlled oscillator 101 by the phase comparison circuit 103, the resistors 104, 106 and 107 forming the loop filter, the capacitor 105 and the amplifier 102. is there. Here, the loop filter is configured such that a transistor 108 is provided in series with the resistor 106, and the base of the transistor is ON / OFF controlled via the AND circuit 110 and the resistor 109. The servo circuit 22 is a circuit for controlling the tape feed and the number of rotations of the cylinder. When 21F is 0, fast feed is performed, and when 21R is 0, rewinding is performed. Further, 21S is a signal for controlling the play state to the stop state, and these control signals are controlled by the microcomputer 21. In the above configuration, since 21F and 21R are both 1 in the normal play state, the AND circuit 110 becomes 1 level and the transistor 108 becomes ON, forming a loop filter. Resistance 1
A resistor 106 is inserted in parallel with 07. Therefore, since the resistor 104 does not change, the gain in the high frequency band is reduced and the capture range is reduced, but the phase shift due to noise in the high frequency band does not occur, and the bit synchronization circuit has a good error rate. Further, at the time of fast-forwarding and rewinding, one of 21F and 21R becomes 0 level, so that the transistor 108 becomes O
FF. Therefore, the lag lead filter is formed by the resistors 104 and 107 and the capacitor 105. This means that the gain in a wide range is increased as compared with the normal reproduction, and the capture range is expanded. At the time of high-speed search, it is not necessary to faithfully reproduce the music signal, but it is necessary to read out the control signal without fail. By widening the capture range, data can be captured without malfunction.

FIG. 2 is a diagram showing a head locus during high-speed search according to the present invention. Tracks 30B, 31A, recorded on the tape 3 are shown in FIG.
... Head 2A traces 33A while crossing as shown in the figure. 30B, 31B, ... Are not reproduced because the azimuth angles are different, and 30A, 31A, 32A ... Can be read by the head 2A.

FIG. 3 is a diagram showing the timing of the signals read by the head 2A, and the track signals of 30A ... 39A can be reproduced with respect to the cylinder rotation. In this, the recorded control signal is read out, and the reproduction signal processing circuit 16 and the microcomputer 21 determine whether the start signal of the desired music is detected.

FIG. 4 is a timing chart during the search operation of FIG. 1, in which the microcomputer 21 sets 21S, 21R, and 21F to 1 level to bring them into a play state. Here, to search for songs,
21F is set to 0 level and high speed fast forward operation is performed. The signal processing circuit 16 reads the control signal, and at the timing 16S when the start signal of the desired music is detected, the microcomputer 21 sets 21F to 1 and stops the fast-forward operation. To correct the tape overrun, set 21R to 0 and rewind until the beginning signal of the song is detected again. Therefore, the AND circuit 110 can be set to 0 during the search operation, and the capture range can be expanded during the search operation.

FIG. 5 shows that in the embodiment of FIG.
FIG. 6 is a characteristic diagram showing the relationship between the value of the resistor 107 and the capture range when is turned off. Thus, the larger the value of the resistor 107, the wider the capture range. Therefore, in the present invention, the value of the resistor 107 is set to a large value so that a desired capture range can be obtained during a high speed search in which the transistor 108 is turned off.

Similarly, FIG. 6 is a characteristic diagram showing the relationship between the value of the resistor 107 and the error rate when the transistor 108 is turned off. In this way, contrary to the case of the capture range, the error rate deteriorates as the value of the resistor 107 increases. However, the normal capture does not require a wider capture range than the high-speed search. Therefore, in the present invention, paying attention to this point, the transistor 10 turned on and the resistor 10 connected in parallel with the resistor 107 is connected.
The value of 6 was set small. This makes it possible to optimize the error rate during normal reproduction.

As described above, according to the present invention, during play and high-speed search,
By providing a circuit that switches the loop filter,
During normal playback, you can play back with a good error rate, you can faithfully play back music signals, and during high-speed search, the capture range is expanded and the fluctuations in the data transmission speed are followed, without error.
Since the PLL circuit can be locked, the control signal can be detected without malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram of a rotary head type magnetic recording / reproducing apparatus according to the present invention, FIG. 2 is a diagram showing a head locus during high-speed search, and FIG. 3 is a diagram showing reproduced signals during high-speed search. FIG. 5 is a timing diagram of FIG. 1, FIG. 5 is a diagram showing the capture range of FIG. 1, and FIG. 6 is a diagram showing the error rate of FIG. 15 …… bit synchronization circuit, 16 …… playback signal processing circuit, 21 …… microcomputer, 22 …… servo circuit, 110 …… and circuit, 108 …… transistor

Claims (3)

[Claims] 1. Means for recording and reproducing a digital signal on a recording medium, and data for normal reproduction from the recording medium,
In a digital signal reproducing apparatus having means for intermittently taking out data and for fast-forwarding reproduction, a phase locked loop circuit for taking out reproduced data and performing bit synchronization, and a first capture range characteristic of the phase locked loop circuit Means for switching between the range characteristic and a second capture range characteristic wider than the range;
When the normal reproduction is changed to the fast-forward reproduction by the fast-forward reproduction means, the capture range characteristic of the phase-locked loop circuit is changed from the first capture range characteristic to the first capture range characteristic by the switching means in synchronization therewith. A bit synchronization circuit characterized by switching to a second capture range characteristic. 2. The bit synchronization circuit according to claim 1, wherein the switching means is configured to switch a loop gain in a high frequency band of the phase locked loop circuit. 3. The phase-locked loop circuit includes a lag lead type loop filter, the loop filter being connected between a first resistor connected between its input and output terminals and an output terminal and a reference potential. A series circuit of a capacitor and a second resistance, and a series circuit of a third resistance and a switch connected in parallel to the second resistance, and the switching means closes the switch during normal reproduction, The bit synchronization circuit according to claim 1 or 2, wherein the switch is opened when the reproducing means is operated.