JPH0770500B2 - Electrode / wiring manufacturing method - Google Patents
Electrode / wiring manufacturing methodInfo
- Publication number
- JPH0770500B2 JPH0770500B2 JP60052209A JP5220985A JPH0770500B2 JP H0770500 B2 JPH0770500 B2 JP H0770500B2 JP 60052209 A JP60052209 A JP 60052209A JP 5220985 A JP5220985 A JP 5220985A JP H0770500 B2 JPH0770500 B2 JP H0770500B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- tisi
- electrode
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は大規模集積回路に使用される電極・配線の製造
方法に関するものであり、特に窒素またはアンモニアガ
ス中で容易に窒化可能な金属の微細シリサイド電極の形
成に好適な電極・配線の製造方法に関する。Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing electrodes / wirings used in large-scale integrated circuits, and particularly to fine metal particles that can be easily nitrided in nitrogen or ammonia gas. The present invention relates to an electrode / wiring manufacturing method suitable for forming a silicide electrode.
従来、金属シリサイド電極・配線の形成方法としてはC.
Y.Ting and M.Wittmer;J.Appl.Phys.54 937（1983）が
知られている。Conventionally, C. is the method of forming metal silicide electrodes and wiring.
Y. Ting and M. Wittmer; J. Appl. Phys. 54 937 (1983) are known.
上記公知例に従い、TiSi2を形成してみるとTiO2は形成
されなかったがTiSi2表面が荒れ、凸凹しており、ま
た、開孔したコンタクトからTiSi2がはみ出して成長し
ているのが観察された。According to the above-mentioned known example, when TiSi 2 was formed, TiO 2 was not formed, but the TiSi 2 surface was rough and uneven, and TiSi 2 was protruding and growing from the opened contact. Was observed.
〔発明の目的〕 本発明の目的は表面の荒れがなく、また、開孔したコン
タクトからTiSi2がはみ出して成長することのない自己
整合的な金属シリサイド電極の形成方法を提供すること
にある。[Object of the Invention] It is an object of the present invention to provide a method for forming a self-aligned metal silicide electrode that has no surface roughness and does not grow by protruding TiSi 2 from an opened contact.
本発明者の検討によれば、TiSi2の形成を窒素またはア
ンモニア雰囲気で行うと、TiSi2形成中にTiの表面にはT
iNが形成され、TiSi2表面の荒れ、コンタクトにおけるT
iSi2の横方向成長が防止できることがわかった。しか
も、TiNのエツチングはH2O2−NH4OH系のエツチング液で
容易に行なうことができ、TiSi2はエツチングされない
ため、TiSi2のみをコンタクト部に残すことが可能であ
る。According to the study by the present inventor, when TiSi 2 is formed in a nitrogen or ammonia atmosphere, T is not formed on the surface of Ti during TiSi 2 formation.
iN is formed, roughness of TiSi 2 surface, T at contact
It was found that lateral growth of iSi 2 can be prevented. Moreover, etching of TiN can be easily performed with an H 2 O 2 —NH 4 OH-based etching liquid, and since TiSi 2 is not etched, only TiSi 2 can be left in the contact portion.
第１図乃至第３図は本発明の一実施例を示したものであ
る。第１図に示すように１Ωcmのｐ型Si基板１に形成し
たMIS型電界効果型トランジスタのソース７、ドレイン
８上のSiO2をエツチング除去後、Ti6を0.15μｍの厚さ
に堆積させる。２はゲート酸化膜、３は素子分離用のSi
O2、４はゲート電極、５はPSGである。次に第２図に示
すようにこの試料を600℃の窒素またはアンモニア雰囲
気中で加熱して厚さ70nmのTiSi29をソース、ドレイン上
に形成するとともにTiの表面にはTiN10を形成する。次
に第３図に示すようにH2O2−NH4OH溶液中にこの試料を
浸漬するとTi6およびTiN10が溶解して除去され、ソー
ス、ドレイン上にはTiSi210のみが自己整合的に残る。
この方法で形成したTiSi2電極の表面は滑らかであり、
凹凸は見られなかつた。また、ソース、ドレインからの
TiSi2のはみ出しも見られなかつた。1 to 3 show an embodiment of the present invention. As shown in FIG. 1, the SiO 2 on the source 7 and the drain 8 of the MIS field effect transistor formed on the p-type Si substrate 1 of 1 Ωcm is removed by etching, and then Ti 6 is deposited to a thickness of 0.15 μm. 2 is a gate oxide film, 3 is Si for element isolation
O 2 , 4 is a gate electrode, and 5 is PSG. Then the Ti surface to form a TiSi 2 9 heated with a thickness of 70nm this sample as shown in FIG. 2 in a nitrogen or ammonia atmosphere at 600 ° C. source, on the drain forming the TiN10. Next, as shown in Fig. 3, when this sample was dipped in a H 2 O 2 —NH 4 OH solution, Ti6 and TiN10 were dissolved and removed, and only TiSi 2 10 was self-aligned on the source and drain. Remain.
The surface of the TiSi 2 electrode formed by this method is smooth,
No irregularities were seen. Also, from the source and drain
No protrusion of TiSi 2 was seen.
以上説明したごとく本発明によれな、簡単なプロセスで
自己整合的な微細電極を形成できるため、特に低抵抗電
極・配線として有望なTiSi2の大規模集積回路への適用
が容易に可能となる。シリサイドとしては本発明に用い
たTiの他にZr,Hf,V,Nb,Ta,Crシリサイドも用いることが
できる。As described above, according to the present invention, since a self-aligned fine electrode can be formed by a simple process, it can be easily applied to a large-scale integrated circuit of TiSi 2 which is particularly promising as a low resistance electrode / wiring. . As the silicide, Zr, Hf, V, Nb, Ta or Cr silicide can be used in addition to Ti used in the present invention.
第１図乃至第３図は本発明の一実施例におけるMOSトラ
ンジスタの製造工程を示す素子の断面説明図である。 図中、１……Si基板、２……ゲート酸化膜、３……フイ
ールド酸化膜、４……ゲート電極、５……PSG、６……T
i、７……ソース、８……ドレイン、９……TiSi2、10…
…TiN。1 to 3 are cross-sectional explanatory views of an element showing a manufacturing process of a MOS transistor in one embodiment of the present invention. In the figure, 1 ... Si substrate, 2 ... gate oxide film, 3 ... field oxide film, 4 ... gate electrode, 5 ... PSG, 6 ... T
i, 7 ... Source, 8 ... Drain, 9 ... TiSi 2 , 10 ...
… TiN.
Claims (1)
上に形成する工程と、上記半導体基板の露出された表面
上から上記絶縁膜上に延伸する金属膜を形成する工程
と、窒素若しくはアンモニアガス雰囲気中で熱処理する
ことにより、上記金属膜と上記半導体基板の露出された
表面が接する部分には上記金属のシリサイド膜を、上記
金属膜の露出された表面上には上記金属の窒化物膜をそ
れぞれ形成して、上記絶縁膜上には上記窒化物膜と上記
金属膜からなる二層膜を、上記半導体基板の露出された
表面上には上記シリサイド膜、上記金属膜および上記窒
化物膜からなる三層膜をそれぞれ形成する工程と、上記
窒化物膜および上記金属膜を除去して、上記シリサイド
膜を上記半導体基板の露出された表面上に選択的に残す
工程を含むことを特徴とする電極・配線の形成方法。1. A step of forming an insulating film having an opening on a surface of a semiconductor substrate; a step of forming a metal film extending from the exposed surface of the semiconductor substrate onto the insulating film; By heat treatment in an atmosphere of ammonia gas, a silicide film of the metal is formed on a portion where the metal film contacts the exposed surface of the semiconductor substrate, and a nitride of the metal is formed on the exposed surface of the metal film. A film is formed on the insulating film, and a two-layer film including the nitride film and the metal film is formed on the insulating film, and the silicide film, the metal film, and the nitride film are formed on the exposed surface of the semiconductor substrate. And a step of removing the nitride film and the metal film to selectively leave the silicide film on the exposed surface of the semiconductor substrate. Method for forming electrodes and wiring to be.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052209A JPH0770500B2 (en) | 1985-03-18 | 1985-03-18 | Electrode / wiring manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052209A JPH0770500B2 (en) | 1985-03-18 | 1985-03-18 | Electrode / wiring manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61212041A JPS61212041A (en) | 1986-09-20 |
| JPH0770500B2 true JPH0770500B2 (en) | 1995-07-31 |
Family
ID=12908371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60052209A Expired - Lifetime JPH0770500B2 (en) | 1985-03-18 | 1985-03-18 | Electrode / wiring manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770500B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1306072C (en) * | 1987-03-30 | 1992-08-04 | John E. Cronin | Refractory metal - titanium nitride conductive structures and processes for forming the same |
| US4920073A (en) * | 1989-05-11 | 1990-04-24 | Texas Instruments, Incorporated | Selective silicidation process using a titanium nitride protective layer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5846631A (en) * | 1981-09-16 | 1983-03-18 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPS61142739A (en) * | 1984-12-17 | 1986-06-30 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-03-18 JP JP60052209A patent/JPH0770500B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| Ｉ．Ｂ．Ｍ．ＴｅｃｈｎｉｃａｌＤｉｓｃｌｏｓｕｒｅＢｕｌｌｅｔｉｎ２５〔１２〕，Ｐ．６３９８〜６３９９ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61212041A (en) | 1986-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |