JPH0770587B2 - Method for manufacturing semiconductor integrated circuit structure - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit structure, and more particularly, it uses a common semiconductor substrate as a starting material, but finally, a plurality of independent block-shaped or island-shaped semiconductors. The present invention relates to a method for obtaining a semiconductor integrated circuit structure which can be viewed as an aggregate structure of regions.

[0002]

2. Description of the Related Art Generally, a plurality of electrically independent regions are provided in a block shape or an island shape on a semiconductor substrate which is generally supplied as a semiconductor wafer, and an electronic element (of course, an electronic circuit is also included in each individual area). In the case of obtaining a semiconductor integrated circuit structure in which (a) is formed, the most common method of electrically separating the individual regions is so-called pn junction separation, as is well known. But,
This method is often not suitable depending on the type of electronic device built in each individual area. For example, when a high breakdown voltage element is integrated, the pn junction does not have a breakdown voltage, and when a photoelectric conversion element is integrated, a pn junction is formed on the surface opposite to the integration surface side. A photocurrent due to light easily flows between the element and the substrate, and good separation characteristics cannot be obtained.

On the other hand, a device as shown in FIG. 11 has been made. That is, at least a part of the semiconductor substrate 10 is thinned, and separation regions (p regions in the case shown) 12, ... A region 13 (n region in the case shown) between the adjacent isolation regions 12 and 12 is used as an element formation region 13.

[0004]

According to the method shown in FIG. 11, the electrical isolation between the adjacent element forming regions 13, 13 can be relatively satisfactory. However, no matter how much the semiconductor substrate 10 is thinned,
It is not always easy to form the separation regions 12, ... so as to pass through both the front and back main surfaces of the thin layer portion 11.
It wasn't efficient either. For example, the separation region 12, ...
Is generally formed by impurity diffusion, but this takes a considerably long time and it is difficult to reduce the manufacturing cost. In addition, even if measures are taken to suppress the lateral diffusion of impurities,
Since it cannot be completely eliminated, as the diffusion distance in the depth direction becomes longer, the diffusion distance in the lateral direction cannot be ignored, and eventually the area of the element formation region 13 is narrowed, and the integration density of the entire element is reduced. There was a drawback that caused it. In other words, this means that it was difficult to make the distance between adjacent individual regions (element formation regions) significantly smaller than the thickness, and it was also difficult to form an extremely large number of individual regions. To do. In view of such circumstances, the present invention provides a semiconductor substrate with a plurality of electrically independent regions, or when forming a plurality of individual regions well separated from each other,
It is an object of the present invention to provide a new manufacturing method that is simple and efficient, and can also arrange a large number of individual regions at intervals that are significantly shorter than the thickness, if necessary.

[0005]

In order to form a plurality of individual regions electrically isolated from each other on a semiconductor substrate, in the present invention, as the semiconductor substrate, any one of surface indices a, b and c is used. A semiconductor substrate having crystal planes (a, b, c) whose both main surfaces are the same or substantially the same as each other, one of which is 0 or nearly 0 and the other two absolute values are not 0 or substantially 0. To use. Here, “nearly 0” and “substantially the same” means surfaces having a deviation within a range of, for example, about 10 degrees in the direction of each axis from the crystal planes represented by the respective surface indices a, b, and c. However, it is called a crystal plane (a, b, c). Further, a thin film containing atoms having a smaller atomic number than the constituent atoms of the semiconductor substrate at a concentration of 10 ¹⁹ atoms / cm ³ or more is provided on one main surface of such a semiconductor substrate. Then, toward the thin film from the main surface side facing the main surface provided with this thin film, by performing selective etching on the semiconductor substrate in the thickness direction, at least the semiconductor substrate is pulled out to the front and back, Grooves leading to the thin film are formed, thereby forming a plurality of individual regions separated from each other by such grooves. However, in the above etching, each crystal plane (d, e,
f) and (g, h, i) each surface index d, e, f comrades, and g, h, i comrades have the same or almost the same absolute value, but dg, eh, fi Choose to be negative in each relationship. The meaning of being almost the same here also means that a slight deviation is allowed.
In addition to the basic aspect based on such a group of basic requirements, the present invention also further includes a step of forming one or more other layers between the main surface of the semiconductor substrate and the above-mentioned thin film,
There is also proposed a method in which the formation of the groove by the above-mentioned etching is completed in any one of the one or more other layers instead of reaching the thin film.

[0006]

FIG. 1 shows an example of a sectional structure of a semiconductor integrated circuit structure manufactured according to the present invention. Although this is an integration of photoelectric conversion elements, an example of the manufacturing process thereof is shown in order from FIG. 2 onward, so the description will be started first with reference to FIG. 2 onward.

An n-type silicon substrate 20 is prepared as a starting member, and its main surface has a crystal plane of, for example, (1, 1,
0), (2,2,0) and the like. As will be described in advance, when the crystal planes of the main surface of the semiconductor substrate 20 are generally expressed as (a, b, c), any one of the surface indices a, b, c is 0. , The remaining two surfaces having the same absolute value other than 0 are selected as the main surface. That is, a = 0; | b | = | c | ≠ 0; or b = 0; | c | = | a | ≠ 0; or c = 0; | a | = | b | ≠ 0; . However, as described above, with respect to the main surface crystal plane,
The deviation with respect to each crystal axis direction can be allowed within a range of, for example, about 10 degrees, and therefore the above equal sign can be converted into a so-called near-equal (approximately equal) symbol.

After forming oxide films 31 and 32 for protection on both the front and back main surfaces of the semiconductor substrate 20, a predetermined oxide film 31 is formed on one main surface (hereinafter referred to as the front surface). An opening is formed according to the pattern, and appropriate impurities such as boron having an atomic number smaller than that of silicon are diffused to form a relatively large area of the first p-type region 21 and as will be described later. A relatively narrow second p-type region 51, which may be a lattice as a whole in planar shape, is formed, and the second p-type region 51 is formed by the adjacent first p-type region 21, Located between 21.

The first p-type region 21 is a functional region for exhibiting a photoelectric conversion function between itself and the semiconductor substrate 20, and may have an impurity concentration suitable for this, but the second p-type region 21. Since 51 finally becomes a thin film portion that physically supports between the adjacent semiconductor individual regions, at least the concentration of impurities constituting the second p-type region, for example, the boron concentration assumed in this case is 10 ¹⁹ pieces / cm ³ or more. Therefore, the second p-type region 51 can also be expressed as a p ⁺ -type region as shown in the figure, but the lower limit of the density corresponds to about 0.1% in terms of the atomic number ratio with silicon. If it is more than this, the tensile stress of the p ⁺ -type region 51 increases, and even if only this region 51 is left to be etched to become a thin film portion in the future, its thinness provides sufficient mechanical strength. Can be born. Of course, as a result, the functional region 21 that should perform the photoelectric conversion function
In some cases, it is appropriate that the second p-type region 51 has the same boron concentration.

Next, as shown in FIG. 3, the oxide film 31 functioning as a masking layer is removed, and an oxide film 33 is newly formed as another masking layer. The oxide film 33 is provided with an opening that covers the p-type regions 21 and 51 of the semiconductor substrate 20 and exposes the main surface of the semiconductor substrate 20 between them, and appropriate impurities are diffused through the opening to form the n ⁺ -type regions. 22 to form the first p-type region 21 in the future.
A photoelectric conversion mechanism by a pn junction is configured between each one. On the back surface side of the semiconductor substrate 20, after the oxide film 32 (FIG. 2) that has been formed is removed, the n ⁺ layer 23 is formed on the entire back surface.

After that, the oxide film 3 is again formed on both the front and back main surfaces.
After forming 4, 35, as shown in FIG. 4, an opening for contact formation is opened in the oxide film 34 on the front surface side according to a predetermined pattern, and the left end of the first p-type region 21 is moved to the left. The second p-type region 51 is electrically connected to the n-type region 22 located to the left of the second p-type region 51, so that the conductive material is filled in each contact opening. Electrodes 36 are formed to extend over the region 51 along the surface of the oxide film 34. However, in the figure, the n ⁺ -type regions 22 at the left and right ends are provided for conducting the n ⁺ layer 23 on the back surface side to a back surface electrode described later, after passing through the semiconductor substrate 20 itself as a conductive path in the thickness direction. Therefore, the rightmost electrode 36 crosses over the second p-type region 51 and is in contact with both of the n ⁺ type regions 22 and 22 located on both sides of the region 51.

Next, as shown in FIG. 5, in the portions located below the surface side n ⁺ type regions 22, 22 at the left and right ends,
An opening is formed in the oxide film 35 on the back surface side so that the conductive material is filled in the opening, and a pair of back surface electrodes 37,
37 is formed. The material for forming the electrodes or the conductive material is the same as that of the electrodes 36 on the front surface side, but is not particularly limited, and may be used in this kind of semiconductor circuit construction technology. Any material can be used.

As described above, the front and back electrodes 36, 37
6 is formed, an adhesive 38 is used on the front surface side to form a transparent member for protecting the front surface (light receiving surface), as shown in FIG.
For example, quartz glass 39 is bonded. Of course, various adhesives 38, which have high transparency themselves and are considered appropriate in view of the difference in coefficient of thermal expansion, have been provided in recent years, and thus can be arbitrarily used.

Next, as shown in FIG. 7, the semiconductor substrate 2
0 from the back surface side to the front surface side, especially each second p-type region 5
Etching towards 1, ..., narrow groove 40, ...
.. is formed. The groove 40 is cut through the semiconductor substrate 20 so as to end at a position reaching each second p-type region 51 (actually, a position slightly cutting into the region 51). However, in this etching, the crystal faces parallel to each other, which are the opposite side faces of the formed groove 40, are (d, e,
f), (g, h, i), the respective surface indices d, e, f, and g, h, i have the same absolute value, but dg, eh, fi. In the product relation, the surface is chosen to be negative. That is, | d | = | e | = | f |, | g | = | h | = | i |; dg, eh, fi <0; In the illustrated case, the (1, -1, -1) plane and the (-1,1,1) plane are selected as an example of the case where the above condition is satisfied. However, again, the equal sign above
Even if the symbols are converted into substantially the same symbols, the preferable etching results described below can be obtained, that is, some deviation in each axial direction of the crystal plane can be allowed.

When etching is performed by selecting such a surface, when the semiconductor substrate 20 is, for example, silicon, the thickness of the semiconductor substrate 20 is increased by using an appropriate alkaline etching solution, for example, an etching solution such as KOH or hydrazine. It is possible to form the groove 40 having a width significantly smaller than that of the above. Generally, even if the thickness of the semiconductor substrate 20 provided as a semiconductor wafer is 200 μm, the width of the groove 40 to be formed can be reduced to about 10 μm. Therefore, the adjacent grooves 40,
The size of each block-shaped or island-shaped individual region 41 formed between 40 can be made larger than that in the case where they are separated by the conventional impurity diffusion, and conversely, if the same size is acceptable, the conventional A larger number of individual areas 41
Can be formed. Moreover, the semiconductor substrate 20 is
Since it cuts through all of its thickness, the electrical isolation between the adjacent individual regions 41, 41 is almost complete. Further, in such etching, the region 51 of the portion corresponding to the bottom of the groove 40 contains as an impurity an atom having an atomic number smaller than that of silicon, for example, as shown in the above-mentioned embodiment, boron-doped p (p ⁺ ) type. In the region 51, the etching rate in the region 51 is extremely low with respect to the etching in the above direction, so that this can also function as an etching stopper.

Further, in the above embodiment, the second p (p ⁺ )
The mold region 51 is left as the thin film portion 51 as a result of etching. However, as described above, if the impurity concentration of boron or the like added to the mold region 51 is 10 ¹⁹ pieces / cm ³ or more, mechanical tensile stress is also generated. Sufficient, adjacent individual areas 41, 4
The power to physically support 1 is also created.

However, the groove 40 formed in this way
The interior may be filled with a suitable insulating material, which of course greatly increases the mechanical strength. Of course, as can be seen from this embodiment, when the quartz glass 39 is provided on the surface of the semiconductor substrate 20 with the adhesive 38, sufficient practical strength can be obtained.

In this embodiment, by further filling the groove 40 with an insulating material 42 from the step shown in FIG. 7,
An attempt is made to complete an integrated structure of a photoelectric conversion element as a target semiconductor integrated circuit structure, and a cross section of the completed state is shown in FIG. As is apparent, in the cross section shown in the figure, the three individual regions 41 in the middle are the device formation regions 43.
In each of the element formation regions 43, a p-type region (which may be a p ⁺ -type region as described above) 21 and an n ⁺ -type adjacent to the right side of the one main surface side are formed. A photoelectric conversion function portion is formed by a pn junction with the region 22, and these adjacent pn junctions are further formed by the electrodes 36, ...
Are connected in series with each other. On top of that,
The individual regions 41, 41 located at the left and right ends are lead-out terminal formation regions 44, 44 to the external circuit, and the electrodes 36, 36 on the front surface side are different from the electrodes on the back surface side. 37 and 37 are electrically connected via the semiconductor substrate 20 itself. In other words, the voltage generated by the light incident on the semiconductor substrate 20 through the transparent member 39 can be obtained between the pair of back electrodes 37, 37 thus provided, and The generated photocurrent can be taken out. The individual region 41 that functions as the lead-out terminal forming region 44 still has an electronic element called an electric line incorporated therein.

However, the formation of the etching groove 40 according to the limiting requirements of the present invention is also possible when viewed in a cross section orthogonal to the cross section shown in FIGS. That is, as shown in FIG. 8, a plurality of individual regions 41, ... It is possible to obtain a structure in which ... are arranged. If a photoelectric conversion circuit as shown in FIG. 1 is mounted in each of the individual areas 41, ..., To improve the open circuit voltage,
It is possible to obtain a structure in which all the photoelectric conversion circuits formed in all the individual regions 41, ... Are sequentially connected in series by the surface electrodes 36 (FIG. 1). Unlike this, for example, in the x direction, the photoelectric conversion circuits formed in the individual regions 41, ... Arranged in parallel along the direction are serially connected in the same manner as above, but this and Y It is also possible to create the electrode pattern of the lead terminal in the lead terminal forming region 44 so as to be in a parallel relationship with the series photoelectric conversion circuits extending in parallel in the direction of arrangement, and in this case, of course, The capacity of the current generated by light can be increased.

Further, in the cross sections shown in FIGS. 1 to 7, the individual regions 41, 41 as the lead terminal forming regions 44, 44 located on the left and right appear to be independent from each other, but in reality, they are shown in FIG. Via a pair of outer edge portions 44 ', 44' which are orthogonal to and span between them,
The structure is mechanically connected, and eventually the supporting frame 45 is configured as a whole, and in the supporting frame 45, as described above, the individual divided into a plurality of parts in the x direction and the y direction, respectively. Element formation regions 43, ... As regions may be formed. Such a structure is particularly excellent in mechanical strength.

The electronic elements or electronic circuits formed in the element forming regions 43, ... Are essentially arbitrary problems, but depending on the circuit to be formed, the second p ⁺ The thin film portion 51 as the mold region is not provided discretely as in the above embodiment, but may be provided almost all over the surface of the semiconductor substrate. Further, as in the above-described embodiment, the thin film portion 51 has a width of the groove 40 so that one side of the thin film section 51 covers the main surface of the pair of individual regions 41, 41 facing each other with the groove 40 interposed therebetween. Even if it is a partially widened portion, the thin film portion 51 is formed by adding impurities to the semiconductor substrate itself.
Instead of being formed, it may be formed as a separate layer member on the semiconductor substrate and then processed into such a partial member.

The embodiment shown in FIGS. 9 and 10 is also in accordance with the gist of the present invention, except that the thin film 52 does not have only the etching stopper function of the thin film 51 described above. Shows. This is because the oxide film 34 is interposed between the main surface of the substrate and the thin film 52. For the corresponding constituent elements, the reference numerals used in the above-mentioned embodiments are used. First, FIG. 9 shows the structure obtained in the steps up to the etching step according to the present invention. Main surface (a,
b, c) have the surface index relation described in the first embodiment, and therefore the back surface of the semiconductor substrate 20, which is, for example, the (1, 1, 0) surface, is uniformly oxide film 35 in this embodiment.
It is only covered with, and each area and layer structure is concentrated on the surface side. That is, similar to the previous embodiment, the first p-type regions 21, ... Are formed at appropriate intervals on the surface of the n-type semiconductor substrate 20, and between them,
N ⁺ type regions 22, ... Are formed. Then, an oxide film 34 is formed substantially in series on these regions 21 and 22, and a silicon nitride thin film 52 is further formed thereon. Then, the middle two electrodes 3 in FIG.
6, 36 are formed by the same pattern as the electrodes 36, 36 of the previous embodiment, and have a function of connecting pn junctions in series in the future. On the other hand, the electrodes 37 ′ and 37 ′ located at the left and right ends are to be lead-out terminals to an external circuit corresponding to the electrodes 37 and 37 provided on the back surface side of the semiconductor substrate 20 in the previous embodiment. The left electrode 37 'makes ohmic contact only with the p-type region 21, and the right electrode 37' is
Has ohmic contact only with the n ⁺ type region 22, and both have a large area portion in the opposite directions.

With respect to such a structure, a groove 40 is formed by etching the back surface side of the semiconductor substrate 20 in the thickness direction, and the bottom of the groove 40 (located on the front surface side of the semiconductor substrate 20) is the semiconductor substrate. Oxide film 34 formed on the surface side
By doing so, as shown in FIG. 10, block-shaped or island-shaped individual regions 41, ... In which adjacent ones are almost completely electrically separated from each other can be obtained.
Of course, also in this etching, the parallel crystal faces (d, e, f) and (g, h, i), which are the opposite side faces of the groove 40 to be formed, have their respective surface indices d according to the gist of the present invention. , E, f comrades and g, h, i comrades have the same absolute value, but are selected to be negative in the product relation dg, eh, fi. In the case shown, as an example, the (1, -1, -1) plane and the (-1,1, -1) plane
1) Face is selected. Further, as described above, as the solution used for etching, a solution having a strong selectivity in the above surface index relation, for example, an alkaline solution such as hydrazine or KOH is selected, so that the thickness of the semiconductor substrate 20 can be reduced. However, the groove 40 having a sufficiently narrow width can be formed. However, more layers may be interposed between the main surface of the semiconductor substrate 20 and the thin film 52 defined in the present invention, and even if etching is stopped at any one of the layers, The spirit of the invention is satisfied. On the contrary, when the silicon nitride film 52 is directly provided on the main surface of the semiconductor substrate 20 without any intervening layer such as the oxide film 34, this is also an etching stopper. Function as.

Also in the groove 40, as in the previous embodiment, a suitable insulating material is filled in the groove 40.
, Which greatly increases the mechanical strength, but if not, in the case of this embodiment,
The silicon nitride films 52 existing in a series on the oxide film 34 on the front surface side of the semiconductor substrate 20 exhibit sufficient mechanical strength, and each structure until the structure shown in FIG. 10 is supported on another supporting substrate. It is satisfactory to obtain the temporary holding function of the individual area, or to obtain the temporary holding function until the attachment of a suitable transparent member, which is not shown, as in the previous embodiment.
Further, since the silicon nitride film 52 generally has an antireflection function, it is an optimum thin film for obtaining a structure in which photoelectric conversion elements are integrated, as illustrated here.

Also in the case of the embodiment shown in FIG. 10,
In the drawing, the three individual regions 41, ... Excluding both ends are element formation regions 43, while the individual regions 41, 41 located at the left and right ends are lead terminals 37 'to the external circuit. , 3
7'formation regions 44, 44 are provided on the front surface side of the semiconductor substrate 20, unlike the previous embodiment. However, like the first embodiment, the lead terminal may be formed on the back surface side of the semiconductor substrate 20, or conversely,
In the above-described first embodiment, like this second embodiment,
It may be modified to form a lead terminal to an external circuit on the front surface side of the semiconductor substrate 20. Also in the second embodiment shown in FIG. 10, a plurality of individual regions may be formed in each of the x direction and the y direction when seen in a plan view, or the individual regions located at the left and right ends. May also serve as a support frame, as shown in FIG.

The description has been given above according to the embodiment of the present invention.
Structural improvements and modifications other than those defined in the claims of the present invention are free. For example, the electronic element to be formed in the element forming region 43 is an arbitrary problem, and naturally, even if the electrode structure for connecting the electronic elements formed in the adjacent individual regions is required, the position is not always the same. It is not necessary to pass over the thin films 51 and 52 referred to in the present invention, and they may be located below them. In addition, the element formation region 43
In the case of the illustrated embodiment, the element was formed before the etching step, but it may be formed after the etching step. The thin film 51 shown as a silicon thin film containing boron is not limited to the partial film as shown in the drawing, and may cover almost the entire area of the main surface of the semiconductor substrate 20, or vice versa. Thin film 5 shown as a nitride film
2 may be a partial one as seen in the thin film 51. A silicon carbide film may be used instead of the silicon nitride film. Further, when the transparent member 39 is attached, its formation may be performed after the formation of the groove 40. In this case, in particular, the thin film formed by the present invention performs a sufficient temporary holding function.

[0027]

According to the present invention, it is possible to form a groove extending to the front and back surfaces of a semiconductor substrate with a width significantly shorter than the thickness of the semiconductor substrate, and to reduce the area of adjacent individual regions without reducing the area. The degree of integration can be increased. Of course, the electrical separation itself is extremely satisfactory. In addition, even if adjacent individual areas need to be mechanically supported (even if temporarily held) by a fairly thin thin film part, they can respond well and ensure sufficient mechanical strength. You can also do it.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a first example of a semiconductor integrated circuit structure manufactured according to the present invention.

FIG. 2 is an explanatory diagram of a first step in manufacturing the semiconductor integrated circuit structure shown in FIG.

FIG. 3 is an explanatory diagram of a second step following the first step.

FIG. 4 is an explanatory diagram of a third step following the second step.

FIG. 5 is an explanatory diagram of a fourth step following the third step.

FIG. 6 is an explanatory diagram of a fifth step following the fourth step.

FIG. 7 is an explanatory diagram of a sixth step following the fifth step.

8 is an explanatory diagram of a planar configuration example of the semiconductor integrated circuit structure shown in FIG.

FIG. 9 is a cross-sectional view of a second example of a semiconductor integrated circuit structure manufactured according to the present invention in a step immediately before completion.

FIG. 10 is a cross-sectional view of a second example of a semiconductor integrated circuit structure manufactured according to the present invention.

FIG. 11 is an explanatory diagram of one technique conventionally used to fabricate a plurality of individual regions on a common semiconductor substrate.

[Explanation of symbols]

20 semiconductor substrate 21 first p-type region 22 front side n ⁺ type region 23 back side n ⁺ type region 34 front side oxide film 35 back side oxide film 36 front side electrode 37 back side lead terminal electrode 37 'Lead-out terminal electrode 39 transferred to the surface side 39 Transparent member 40 Etching groove 41 Individual area 42 Filling substance in the groove 43 Element formation area as individual area 44 Lead-out terminal formation area as individual area 51 Partially formed Thin film or boron-doped p ⁺ type region 52 Thin film or silicon nitride film formed in series

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yoshiki Mae Yashiki 3-3-12 Fujihashi, Ome City, Tokyo Ome Cosmos Electric Co., Ltd. Takuya Imai (56) Reference JP-A-3-161952 (JP) , A) JP-A-2-7467 (JP, A) JP-A-2-260442 (JP, A)

Claims (9)

[Claims] 1. A method for producing a semiconductor integrated circuit structure by producing a plurality of individual regions, which are electrically isolated from each other and have electronic devices mounted on each, from a common semiconductor substrate; Crystal planes (a, b, c) in which any one of them is 0 or almost 0, and the remaining two absolute values are not 0 or almost 0, and are the same or almost the same as each other (a, b, c) using a semiconductor substrate having both main surfaces; on one side of the both main surfaces of the semiconductor substrate,
A thin film containing atoms having a smaller atomic number than the atoms constituting the semiconductor substrate at a concentration of 10 ¹⁹ atoms / cm ³ or more; provided on the main surface of the semiconductor substrate opposite to the main surface provided with the thin film. From the side, toward the thin film, by performing selective etching in the thickness direction, at least the semiconductor substrate is passed through the front and back to form a groove leading to the thin film, and the plurality of individual pieces separated from each other by the groove are formed. Each of the crystal planes (d, e, f) formed by the etching and serving as opposite side surfaces of the groove orthogonal to the main surface.
And the respective surface indices d, e, f of (g, h, i) and g, h, i have the same absolute value or substantially the same absolute value, but the product dg, eh, fi The relationship is set to be negative in each case; 2. The method for manufacturing a semiconductor integrated circuit structure according to claim 1, wherein the semiconductor substrate is a silicon substrate, the atoms are boron, and the thin film is a silicon thin film containing the boron. A method characterized by: 3. The method for manufacturing a semiconductor integrated circuit structure according to claim 1, wherein the semiconductor substrate is a silicon substrate, the atoms are nitrogen, and the thin film is a silicon nitride thin film. And how to. 4. The method for manufacturing a semiconductor integrated circuit structure according to claim 1, wherein the semiconductor substrate is a silicon substrate, the atoms are carbon, and the thin film is a silicon carbide thin film. And how to. 5. A method of manufacturing a semiconductor integrated circuit structure according to claim 1, 2, 3 or 4, wherein one or more layers are formed between the main surface of the semiconductor substrate and the thin film. Further comprising; terminating the formation of the groove by the etching at any one of the one or more layers without reaching the thin film. 6. A method of manufacturing a semiconductor integrated circuit structure according to claim 1, 2, 3, 4 or 5, wherein the thin film has a pair of individual ones facing each other on both sides of the thin film. Forming a width slightly wider than the width of the groove so as to cover the main surface directed to one side of the region. 7. A method of manufacturing a semiconductor integrated circuit structure according to claim 1, 2, 3, 4 or 5, wherein the thin film is formed in series on substantially the entire main surface of the semiconductor substrate. A method characterized by: 8. The method according to claim 1, 2, 3, 4, 5, 6 or 7.
A method of manufacturing a semiconductor integrated circuit structure according to claim 1, further comprising the step of electrically connecting the electronic elements formed in the plurality of individual regions to each other by a wiring pattern extending over the thin film. How to characterize. 9. A method of manufacturing a semiconductor integrated circuit structure according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein at least one of the plurality of individual regions is connected to an external circuit. Forming a lead-out terminal of the above.