JPH0770608B2 - CMOS type semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a CMOS type semiconductor device having a single well structure. Here, the CMOS type means one using a complementary insulated gate transistor.

〔Overview〕

The present invention relates to a CMOS semiconductor device including an output buffer composed of a CMOS transistor having a single well structure arranged around a chip, in which a MOS transistor formed in a well is replaced with a MOS transistor formed in a substrate. By arranging it outside the chip, the latch-up phenomenon caused by noise is suppressed.

[Conventional technology]

Conventionally, in this type of semiconductor device, as shown in FIG. 4, a CMOS output buffer P-channel transistor 2 formed in an N well 1 and a CMOS output buffer N-channel transistor formed in a P-type substrate 6 are used. It was placed inside 3. This is because the ground wire is arranged outside the chip as a countermeasure against static electricity from the outside of the device.

[Problems to be solved by the invention]

In the conventional CMOS semiconductor device described above, as shown in FIG. 4, since the P-channel transistor 2 is arranged adjacent to the internal region 4 of the device, a latch-up phenomenon easily occurs due to current noise. There are drawbacks.

The reason will be described below with reference to the schematic cross-sectional view shown in FIG. The current gain h _{FE of the} P-N-P parasitic bipolar transistor formed by the drain region (P type) of the P channel transistor 2 formed in the N well 1, the N well (N type), and the substrate (P type) Is large, it is very weak against current noise flowing into the semiconductor device from the external output terminal directly connected to the drain region of the P-channel transistor 2. The drain region of the P-channel transistor 2 functions as the emitter of the P-N-P parasitic bipolar transistor, and the positive charge 9 injected into the N-well 1 reaches the inside of the semiconductor device by the bipolar transistor operation, and the P-type substrate 6 The potential rises and the latch-up phenomenon occurs.

Contrary to the above description, in the case of a CMOS output buffer having a P-well structure, the drain of the N-channel transistor formed in the P-well functions as the emitter of the N-P-N parasitic bipolar transistor, so that the semiconductor device The latch-up phenomenon easily occurs with respect to the current noise flowing out of the device.

That is, since the parasitic bipolar transistor having the drain of the MOS transistor formed in the well as the emitter has a vertical structure, its h _FE is the parasitic bipolar transistor of the horizontal structure having the drain of the MOS transistor formed in the substrate as the emitter. Among the transistors that make up the output buffer, the MOS transistor formed in the well is placed adjacent to the internal region because it is larger than the h _{FE of} the transistor. Since the latching phenomenon occurs in the non-applied inner region 4, the latch-up phenomenon is likely to occur with respect to current noise.

The weakness of the CMOS type semiconductor device against the latch-up phenomenon makes it difficult to design a device using the CMOS type semiconductor device. Conventionally, when this type of CMOS semiconductor device is used, a bipolar semiconductor device has been used as an interface between the CMOS semiconductor device and the outside of the device in order to avoid direct current noise particularly from the outside of the device. For this reason, improvements such as cost reduction, power consumption reduction, and device size reduction could not be achieved.

It is an object of the present invention to provide a CMOS type semiconductor device in which the occurrence of the latch-up phenomenon due to noise is suppressed by eliminating the above drawbacks.

[Means for solving problems]

The present invention relates to a CMOS semiconductor including a CMOS-structured output buffer, which is arranged in the periphery of a chip and in which a MOS transistor of one conductivity type formed in a well and a MOS transistor of opposite conductivity type formed in a substrate are combined. In the device, the MOS transistor of one conductivity type formed in the well is arranged outside the chip than the MOS transistor of opposite conductivity type formed in the substrate.

[Action]

By placing the MOS transistor formed in the well on the outside of the chip with respect to the MOS transistor formed in the substrate, a parasitic bipolar transistor with a large current amplification factor h _FE with the drain region connected to the external output terminal as the emitter Since the transistor is moved away from the internal region, the influence of the carrier potential increase due to the injected carriers due to noise does not reach the internal region, and the latching phenomenon is suppressed even in the internal region where latching measures are not sufficiently taken, and noise is suppressed. The effect of can be suppressed.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a main part of the first embodiment of the present invention. In this embodiment, the P-channel transistor 2 forming the CMOS output buffer is formed in the N well 1,
The N-channel transistor 3 is formed in the P-type substrate 6. A CMOS output buffer is formed by pairing one P-channel transistor 21 and one N-channel transistor 3 1. In FIG. 1, the CMOS output buffers are arranged in an array around the chip. The P-channel transistor 2 is arranged outside the N-channel transistor 3 on the chip, that is, on the chip edge 5.

A feature of the present invention is that, in FIG. 1, the P-channel transistor formed in the N-well 1 is arranged closer to the chip edge 5 side than the N-channel transistor formed in the P-type substrate 6.

Next, the latch-up phenomenon in this embodiment will be described with reference to the schematic sectional view for explaining the latching phenomenon shown in FIG. FIG. 2 is a schematic cross-sectional view showing a CMOS output buffer obtained by combining the P-channel transistor 2 and the N-channel transistor 3 of FIG. 1, where S is a source, D is a drain and G is a gate. .

A P-N-P parasitic bipolar transistor formed by the drain (P) of the P-channel transistor 2 formed in the N well 1, the well (N) and the substrate (P) is applied to the drain which is an external output terminal. The rise in the substrate potential due to the positive charge 9 injected by the generated external noise is
Since they are separated by the N-channel transistor 3, the rise of the substrate potential in the internal region 4 is suppressed. The image communication channel transistor 3 is provided with a latching countermeasure, and the latching phenomenon does not occur due to the positive charge injection by the P-N-P parasitic bipolar transistor.
Moreover, the occurrence of the latching phenomenon in the internal area is also suppressed,
As a whole, the occurrence of the latching phenomenon due to external noise is suppressed.

In the conventional CMOS type semiconductor device having the arrangement of MOS transistors as shown in FIG. 4, when a current of 200 mA is applied to the CMOS output buffer from the outside of the semiconductor device, a latch-up phenomenon occurs. However, in this embodiment, from the outside of the semiconductor device
The latch-up phenomenon did not occur even when a current of 500 mA was applied to the CMOS output buffer.

FIG. 3 is a plan view showing an essential part of the second embodiment of the present invention. In this embodiment, unlike the structure shown in FIG. 1, the CMOS type semiconductor device has a P well 7. The N-channel transistor 3 formed in the P-well is the N-type substrate 8
It is arranged outside the P-channel transistor 2 formed inside from the chip edge 5. CM with P-well 7 structure
The OS type semiconductor device is apt to latch up due to the current noise flowing out of the semiconductor device, but the CMOS type semiconductor device using the arrangement shown in FIG.
When the current of 200mA was drawn from the output buffer, the latch-up phenomenon occurred, but even when the current of 500mA was drawn, the latch-up phenomenon did not occur.

The feature of the present invention resides in that the N-channel transistor 3 is arranged at the chip edge 5 rather than the P-channel transistor 2 in FIG.

[Effects of the Invention] As described above, according to the present invention, among the MOS transistors forming the CMOS output buffer, the MOS formed in the well is used.
By arranging the transistor on the outside of the chip with respect to the MOS transistor formed in the substrate, there is an effect of suppressing the latch-up phenomenon due to current noise. In particular, strengthening the CMOS semiconductor device against external current noise not only improves the reliability of the semiconductor device itself, but also facilitates device design using the semiconductor device. Conventionally, when a CMOS type semiconductor device is used, a bipolar type semiconductor device is introduced as an interface between the outside and the CMOS type semiconductor device to protect the CMOS type semiconductor device. If the CMOS semiconductor device of the present invention is used,
The bipolar semiconductor device introduced for the interface as described above is unnecessary, and the cost, size, and reliability of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing an essential part of a first embodiment of the present invention. FIG. 2 is a schematic sectional view of the main part thereof. FIG. 3 is a plan view showing an essential part of the second embodiment of the present invention. FIG. 4 is a plan view showing a main part of a conventional example. FIG. 5 is a schematic sectional view of the main part. 1 ... N well, 2 ... P-channel transistor, 3 ...
... N-channel transistor, 4 ... internal region, 5 ... chip edge, 6 ... P type substrate, 7 ... P well, 8 ...
N-type substrate, 9 ... Positive charge.

Claims (1)

[Claims] 1. A MOS transistor of one conductivity channel type formed in a well of a conductivity type opposite to that of a substrate disposed around a chip and a MOS transistor of an opposite conductivity channel type formed in the substrate.
In a CMOS semiconductor device including a CMOS-structured output buffer in which a MOS transistor is combined, the one-conductivity-channel-type MOS transistor formed in the well is better than the opposite-conductivity-channel-type MOS transistor formed in the substrate. CMOS type semiconductor device characterized in that it is also placed near the periphery of the chip.