JPH0770611B2 - Manufacturing method of complementary MOS semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a complementary MOS semiconductor device, and more particularly to a method for introducing impurities into a contact hole for taking out an electrode.

[Conventional technology]

In recent years, various planar margins have become smaller with the miniaturization and high-density integration of complementary MOS semiconductor devices, and the junction depth of P and N diffusion layers formed on the main surface of a semiconductor substrate has also become shallow. There is. Therefore, when connecting an electrode to this type of diffusion layer, a contact hole is opened at the location of the insulating film corresponding to the P and N diffusion layers, and then impurities of the same conductivity type as each diffusion layer are added. The structure is introduced into the contact hole by self-alignment to prevent short circuit between the electrode and the semiconductor substrate due to junction breakage which is likely to occur in the contact hole portion.

Therefore, when forming this structure in a conventional complementary MOS semiconductor device, one channel side, for example, the P channel side is covered with a mask material after the contact hole is formed, and N type impurities are ion-implanted into the N channel side contact hole. Therefore, there is a need for a method of introducing P-type impurities into the P-channel side by ion implantation while covering the opposite N-channel side with a mask material.

[Problems to be solved by the invention]

In the conventional method of introducing impurities into the contact holes described above, since the main surface of the semiconductor substrate is covered with the interlayer insulating film or the resist layer for the mask at the time of ion implantation of impurities, the surface is charged by the energy at the time of ion implantation. However, there is a problem that the gate electrode and the semiconductor substrate are short-circuited due to electrostatic breakdown of the gate insulating film, or the interlayer insulating film itself is electrostatically destroyed and the wiring electrode and the semiconductor substrate are short-circuited.

It is an object of the present invention to provide a manufacturing method capable of preventing a short circuit accident due to electrostatic breakdown of an insulating film and manufacturing a highly reliable complementary MOS semiconductor device.

[Means for solving problems]

A method of manufacturing a complementary MOS semiconductor device according to the present invention comprises a step of forming a contact hole facing a PN junction formed in a semiconductor substrate in an interlayer insulating film, and a step of forming a polysilicon layer on the contact hole and the interlayer insulating film. And a step of making the polysilicon layer have conductivity by diffusing impurities contained in the interlayer insulating film and a step of introducing impurities into the contact hole portion by an ion implantation method, without charging the insulating film. Ions can be implanted into the contact hole.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 to 3 are longitudinal sectional views showing main steps of one embodiment of the present invention.

In FIG. 1, an N well 2 is formed on a main surface of a P type semiconductor substrate 1, a field insulating film 3 for element isolation is formed, and then a gate electrode 4 of a MOS type FET is formed on this field insulating film 3, and a semiconductor is further formed. It shows a state in which an N-type diffusion layer region 5 forming a source / drain of an N-channel MOS transistor and a P-type diffusion layer region 6 forming a source / drain of a P-channel MOS transistor are formed on the main surface of the substrate 1. . Reference numeral 7 is an interlayer insulating film made of PSG reflowed by heat treatment, in which contact holes 8 and 9 are provided corresponding to the P-type diffusion layer region 6, the N-type diffusion layer region 5 and the gate electrode 4, respectively. ,
Has opened 10.

Then, as shown in Fig. 2, a thin polysilicon layer is formed on the entire surface.
Put on 11. The thickness of the polysilicon layer 11 is 100 to 1000.
Å is suitable. Then, phosphorus contained in the interlayer insulating film 7 is thermally diffused into the polysilicon layer 11 and further heat treated to lower the specific resistivity. A suitable heat treatment temperature is 700 to 900 ° C., which is a temperature at which the interlayer insulating film 7 does not reflow.

Then, in order to introduce an impurity portion into the contact portion, only the P channel side is covered with the resist mask 12, phosphorus of N type impurity is ion-implanted, and the N type diffusion layer region 5 is deeper than the second N type diffusion layer. A region 13 is formed.

Similarly, as shown in FIG. 3, the N-channel side is covered with a resist mask, P-type impurity boron is implanted, and a second P-type diffusion layer region 15 deeper than this is formed in the P-type diffusion layer region 6. Form.

In any of the above-mentioned ion implantations, the dose amount is set so that the ion concentration of the ions on the surface of the contact portion is 10 ²⁰ or more with the energy that ions sufficiently penetrate the polysilicon layer 11.

After the above steps, a metal or polysilicon film for electrodes is formed as usual, and this is etched into a desired pattern to form the P-type diffusion layer region 6 and the N-type diffusion layer region 5.
Electrodes can be formed that are respectively connected to. The polysilicon layer 11 may be simultaneously etched at the time of this etching to form a body with the electrodes. Alternatively, it may be removed before forming the metal for the electrode.

Therefore, in this manufacturing method, since the entire surface of the semiconductor device is covered with the polysilicon layer 11 having conductivity when the ions are implanted into the contact portion, the insulating film is not charged, and the insulating film at this time is not charged. It is possible to reliably prevent the electrostatic breakdown of the.

In the above example, PSG is used as the interlayer insulating film containing phosphorus.
However, BPSG or a mixture thereof with other glass may be used. Further, the method of depositing the thin polysilicon layer 11 is not limited, and any means such as a CVD method and a sputtering method may be used. Further, the atmosphere for heat treatment for thermally diffusing phosphorus into the polysilicon layer can be freely selected.

〔The invention's effect〕

As described above, according to the present invention, the polysilicon layer is formed on the interlayer insulating film including the contact hole, and the polysilicon layer is made conductive, and then the impurity is introduced into the contact hole portion by the ion implantation method. This polysilicon layer can effectively eliminate the charge accumulated on the surface of the insulating film during ion implantation, and the complementary MOS semiconductor device can be formed without causing electrostatic breakdown in the insulating film. There is an effect that it can be manufactured.

Further, in the present invention, as compared with the case where a metal film is used instead of polysilicon, impurities are not diffused outward even in a heat treatment step for activating impurities in a later step. Incidentally, when the metal film is used, the silicide formed in the contact portion covers the contact, so that the impurity has a low solid solubility in the silicide, so that the impurity diffuses out through the silicide and the contact resistance increases. become. Also, metal ions are not knocked into the substrate due to the knock-on phenomenon during ion implantation. Further, according to the present invention, as compared with the case where polysilicon into which impurities have already been introduced is used, impurities are not diffused into the contact portion during the growth of polysilicon, and the conductivity of the reverse conductivity type in the case of the complementary MOS semiconductor device is reduced. It is possible to suppress an increase in contact resistance of the contact.
Incidentally, when the doped polysilicon is used, the impurities contained during the growth are diffused into the contact portion, and the contact resistance of the contact portion of the opposite conductivity type is increased.

[Brief description of drawings]

1 to 3 are longitudinal sectional views showing an embodiment of the present invention in the order of steps. 1 ... Semiconductor substrate, 2 ... N well, 3 ... Field insulating film, 4 ... Gate electrode, 5 ... N-type diffusion layer region, 6
...... P-type diffusion layer region, 7 ... Interlayer insulation film (PSG), 8,9,1
0 ... Contact hole, 11 ... Polysilicon layer, 12 ...
... resist mask, 13 ... second N-type diffusion layer region, 14 ...
... resist mask, 15 ... second P-type diffusion layer region.

Claims (1)

[Claims] 1. When manufacturing a complementary MOS semiconductor device having an interlayer insulating film containing impurities such as phosphorus, a step of forming a contact hole facing the PN junction formed in a semiconductor substrate in the interlayer insulating film, and the contact hole. And a step of forming a polysilicon layer on the interlayer insulating film, a step of diffusing impurities contained in the interlayer insulating film into the polysilicon layer to make it conductive, and an ion implantation method in the contact hole portion. A method of manufacturing a complementary MOS semiconductor device, comprising the step of introducing an impurity.