JPH0770643B2 - Wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is configured by stacking a plurality of wafers having a plurality of stripe-shaped conductors on the surface thereof, and subjecting them to heat pressure contact to cut the pressure contact body in the axial direction thereof. The present invention relates to a technique for forming a wiring board having a plurality of electrodes made of the conductor and having the same coefficient of thermal expansion in the vertical direction and in the horizontal direction.

[Conventional technology]

The present inventors have previously laminated a plurality of wafers made of, for example, a silicon single crystal having a plurality of striped conductors made of, for example, Al on the surface, and bonded the silicon wafers by interposing Al. We proposed a substrate in which the Al conductor was embedded in the through hole, which was constructed by hot-pressing these wafers and slicing the hot-pressing body in the press-contacting direction.

[Problems to be solved by the invention]

However, with this substrate, the slice (cutting)
Depending on the direction, the coefficient of thermal expansion may differ in the vertical direction and the horizontal direction of the substrate. That is, a silicon wafer is used for the substrate, and for a silicon crystal, for example, in the (111) direction and (10) in the Miller index used to specify the direction of the crystal plane.
It is known that electrical characteristics and chemical properties are different in the direction of (0) (for example, “SCIENCE AND TECHNOLOGY, LS” written by Iwao Sagara, published by Nikkan Kogyo Shimbun on April 25, 1982).
(See “I's story”), and the coefficient of thermal expansion differs depending on the crystal axis, which has an unfavorable effect on the substrate.

It is an object of the present invention to provide a technique capable of matching the thermal expansion coefficients of the above-mentioned substrates in the vertical and horizontal directions.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

In the present invention, during the cutting, the crystal axis in the cutting direction and the crystal axis in the in-plane direction with respect to the cutting direction are made to coincide with each other.

[Action]

As a result, the crystal axes of the substrate in the vertical direction and the crystallographic direction in the horizontal direction match, and the thermal expansion coefficients in these directions can also match.

〔Example〕

 Next, the present invention will be described based on the embodiments shown in the drawings.

Striped Al conductor (1) on the surface as shown in Fig. 2
As shown in FIG. 4, a plurality of silicon wafers (2) having the above are laminated and subjected to thermocompression bonding to form a pressure contact body (3) as shown in FIG. The wafer (2) is generally
An Al wiring (5) is formed on the surface of the wafer body (4) used as a substrate, the wiring (5) is covered with an insulating film (6), and the insulating film (6) is covered with the above-mentioned material. A plurality of Al conductors (1) are arranged in parallel at appropriate intervals. An example of a cross section of the wafer (2) is as shown in FIG. As described above, the wafer main body (4) is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed in this wafer by a well-known technique to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function of a logic circuit and a memory, for example.

The thermocompression bonding is performed under high vacuum at a temperature of 600 ° C. or outside.

As shown in FIG. 5, cutting line (7), the pressure contact body (3)
Cut in the axial direction (pressing direction). After cutting, the substrate is subjected to a polishing process and the like, and a substrate (8) as shown in FIG. 6 and FIG.
Go through.

Incidentally, FIG. 7 shows a state in which the substrate (8) shown in FIG. 6 is laid down.

As shown in FIG. 6, in the thickness direction of the substrate (8), the Al
A plurality of conductors (1) are arranged at appropriate intervals. Since stripe-shaped Al conductors (1) are formed on each silicon wafer (2) as shown in FIG. 4, the Al conductors are stepwise in the vertical direction (A) of the substrate (8). (1) is arranged.

The terminal portion of the Al conductor (1) becomes the pin electrode (9) of the substrate (8).

In the wiring board (8) having the multi-pin electrode (9) as shown in FIG. 7, the Al wiring (5) in FIG.
Serves as internal wiring of the substrate (8).

In such a substrate (8), the coefficient of thermal expansion may be different in the vertical direction (A) and the horizontal direction (B) of the substrate (8).

For example, the coefficient of thermal expansion in the A direction may be larger than that in the B direction, and thermal strain may occur in the substrate (8).

The present invention is intended to solve this problem. For example, when the pressure contact body (3) composed of a plurality of silicon wafers (2) shown in FIG. 1 is cut, for example, the crystal axis in the A direction is (111).
Then, at the time of cutting, the crystal axis in the B direction is also set to the same (111), and the crystal axis in the B direction is appropriately selected and cut so that the both agree with each other. This is the eighth
This will be described in detail with reference to FIGS.

As is well known, for semiconductor crystals, the Miller index is generally used to represent the position and direction of a crystal plane or a crystal axis.

9 (a), (b), and (c) show typical crystal planes (crystal axes) for a cubic lattice crystal. (A) in the figure
Is the (111) plane [[111] axis], and (b) is the (110) plane [[1
10] axis], and (c) shows the (100) plane [[100] axis].

FIG. 10 illustrates the relationship between the crystal plane and the cleavage plane of the wafer body (2) having a (100) plane when scribing on the chip (10) of the silicon wafer body (2).

In a MOS semiconductor integrated circuit, a Si wafer having a (100) plane, that is, a plane whose vector perpendicular to the wafer surface coincides with the [100] direction is generally used. This is a MOS in the (100) plane when compared to other (111) and (110) planes, for example.
This is because the SiO ₂ —Si interface charge density of the transistor is minimized and the most stable interface state is obtained.

Using a (100) Si wafer is also convenient for scribing into square or rectangular chips by utilizing the cleavability of silicon. In the wafer shown in FIG. 10,
As shown in FIG. 10, in the (100) plane, [011], [01
] There are two vectors that are orthogonal to each other. The (011) and (01) planes perpendicular to each vector are the cleavage planes.

The slicing method of the present invention is more apparent from FIG.

FIGS. 8 (a) to 8 (c) show the relationship between crystal planes and crystal axes when the chip (10) is scribed from the silicon wafer (2) as in FIG. 10, and FIG. ), The vertical crystal plane (111) and the horizontal crystal plane (1) of the chip (10) on the right side of FIG.
11) is consistent with. This is possible by aligning the crystal axes as shown in FIGS. 9 and 10. Therefore, in the pressure contact body (3) made of the silicon wafer according to the present invention shown in FIG. By selecting a crystal axis to be cut in the B direction (in-plane direction) that coincides with the crystal axis for the substrate (8), the substrate having the same thermal expansion coefficient in the A direction and the B direction in the substrate (8) is selected. (8) can be obtained.

Next, a structural example of a semiconductor device (multichip module) using the substrate of the present invention will be described with reference to FIG.

In FIG. 11, semiconductor chips (11) are mounted in multiple on the substrate (8) obtained above. The substrate (8) and the chip (11) can be joined by reflowing the solder bumps (12), for example. The semiconductor element (chip) 11 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed in this chip by a well-known technique to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function of a logic circuit and a memory, for example.

The Al conductor (1) of the substrate (8) and the solder bump (12) are connected, and the Al conductor (1) is an Al wiring (inner layer wiring).
The Al wiring (5) is connected to the surface wiring (14) on the surface of the wiring board (13) below the substrate (8) through the Al conductor (1).

The wiring board (13) can also be manufactured by the same method as described above, and has the Al conductor (1) in its thickness direction.

Solder bumps (15) are formed on the back surface of the wiring board (13), and the mounting board (16) such as a printed board and the bumps (15) are reflowed so that they can be mounted.

A cap (17) is attached for sealing the semiconductor chip (11). The cap (17) is made of, for example, a ceramic material.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. Nor.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, a substrate with reduced thermal strain can be obtained, and in the case of a silicon single crystal, the thermal expansion coefficient can be matched with that of a silicon chip, and a multi-chip module with reduced thermal strain can be obtained. Very effective for

[Brief description of drawings]

1 is an explanatory view of an embodiment of the present invention, FIG. 2 is a plan view showing an embodiment of a wafer used in the present invention, FIG. 3 is a sectional view taken along the line II of FIG. 2, and FIG. Is an explanatory view showing an embodiment process of the present invention, FIG. 5 is an explanatory view showing an embodiment process of the present invention, FIG. 6 is a perspective view of a substrate showing an embodiment of the present invention, and FIG. 8 is a perspective view of a substrate showing an example, FIGS. 8 (a) to 8 (c) are explanatory views showing the relationship between crystal axes and crystal planes when a wafer is scribed into chips, and FIG. 9 (a). To (c) are explanatory views of crystal planes and crystal axes with respect to a cubic lattice crystal, FIG. 10 is an explanatory view showing a relationship between a crystal plane and a cleavage plane of a silicon wafer, and FIG. 11 is a substrate of the present invention. It is a structure sectional view of a multichip module. 1 ... Striped conductor, 2 ... Wafer, 3 ... Pressure contact body, 4 ... Wafer body, 5 ... Wiring, 6 ... Insulating film, 7
...... Cutting line, 8 ...... wiring board, 9 ...... electrode, 10 …… chip, 11 …… chip, 12 …… solder bump, 13 …… wiring board, 14 …… surface wiring, 15 …… solder bump, 16… … Mounting board, 17… Cap

Claims (2)

[Claims] 1. A plurality of wafers having a plurality of stripe-shaped conductors on the surface are laminated, heat-pressed, and the press-contacted body is cut in the axial direction thereof, and a plurality of electrodes made of the conductors are provided. In the cutting, the crystal axis of the substrate in the cutting direction and the crystal axis in the in-plane direction with respect to the cutting direction are made to coincide with each other in the cutting, so that the vertical direction and the horizontal direction of the substrate are A wiring board having the same coefficient of thermal expansion. 2. The wiring board according to claim 1, wherein the wafer is made of a silicon crystal and the conductor is made of an Al conductor.