JPH0770684B2 - Capacitors for semiconductor integrated circuits - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement in a capacitor for a semiconductor integrated circuit.

[Outline of Invention]

This invention, in a semiconductor integrated circuit capacitor used for memory cells of dynamic RAM, etc., has a multilayer structure in which a high temperature CVD oxide film formed at a temperature of 700 ° C. or higher and a conductive film are alternately stacked, It has a small thickness, a small occupied area, and a large capacitance.

[Conventional technology]

In recent years, with the increasing integration of semiconductor integrated circuits, dynamics
In a semiconductor integrated circuit capacitor used for a RAM memory cell or the like, the area occupied by the plane is small,
Moreover, it is required to increase only the capacitance. To this end, firstly, the dielectric film thickness should be thinned, but there is a limit to thinning it such as generation of pinholes. Therefore, a conductor film and a dielectric film are provided on the semiconductor substrate,
With a multilayer structure in which the capacitors are alternately stacked, the capacitance can be increased by increasing the effective facing area of the capacitor electrodes. Such a structure can be realized by using a polycrystalline silicon film as a conductor film and using a polycrystalline silicon oxide film obtained by thermally oxidizing the surface of the conductor film as a dielectric film.

[Problems to be solved by the invention]

However, this method has the following drawbacks. First,
When the polycrystalline silicon oxide film is made thin, the withstand voltage is extremely lowered, and the leakage current is large, so the film thickness must be set to 1000 Å or more for practical use. In addition, the polycrystalline silicon film prevents itself from disappearing after thermal oxidation of the surface,
In order to secure a constant film thickness, the film thickness must be practically 2000 Å or more. Therefore, if the multilayer structure is used, the overall thickness of the capacitor becomes very thick, causing disconnection of Al wiring or the like that passes over it. On the contrary, if the number of laminated layers is reduced in order to prevent step breakage, the electrostatic capacity cannot be increased sufficiently, and if each layer is thinned, the dielectric strength and leakage current deteriorate as described above.

[Means for solving problems]

The present invention eliminates the drawbacks when the capacitor for a semiconductor integrated circuit has a multilayer structure, and increases the capacitance per unit occupied area.

For this reason, the present invention is characterized in that the capacitor has a multi-layer structure in which a high temperature CVD silicon oxide film formed at a temperature of 700 ° C. or more and a conductor film are alternately stacked.

[Action]

In this invention, since the dielectric film of the capacitor uses a CVD insulating film instead of a polycrystalline silicon oxide film,
The high temperature CVD silicon oxide film formed at a temperature of 00 ° C or higher has a high dielectric strength even if it is thin, and since the leakage current is small, the dielectric film thickness can be 200 Å or less. Moreover, since it is not a method of oxidizing the conductor film,
Even if a CVD polycrystalline silicon film is used, the film thickness can be reduced to 2000 Å or less. Further, a refractory metal or a silicide thereof can be used for the conductor film for the purpose of reducing the circuit resistance. Therefore, by using a high-temperature CVD silicon oxide film formed at a temperature of 700 ° C. or higher, even if the capacitor has a multi-layer structure, the overall thickness does not become too thick, so that it does not cause disconnection of Al wiring etc. . Therefore, since a multilayer structure can be formed, the capacitance can be increased several times by increasing the number of laminated layers without increasing the occupied area of the capacitor in plan view. Also,
As described above, the dielectric strength and leakage current are excellent.

〔Example〕

 Hereinafter, the details of the present invention will be described with reference to examples.

FIG. 1 is a sectional view of a semiconductor integrated circuit capacitor according to the present invention. The conductor films 13 and 14 are the CVD insulating film 15
For example, they are alternately laminated on the P-type silicon substrate 11 with a space between them. The conductor films 13 are electrically connected to the electrodes 16, respectively, and the conductor films 14 are electrically connected to the electrodes 17, respectively, and are provided on the surface of the substrate 11.
By being electrically connected to the n ₊ diffusion layer 12, a multilayer capacitor is formed. In this structure, the capacitance is determined by the total area of the CVD insulation film sandwiched between the conductor film and the substrate. Therefore, by increasing the number of layers (5 layers in this example) The capacitance can be increased by several times the number of layers. For example, if the thickness of the Al wiring that passes over the capacitor is 1 μm, the conductor film thickness is 2000Å
As a result, even if five layers are laminated, the overall thickness of the capacitor is about Al.

Next, a second method for manufacturing the capacitor according to the present invention will be described.
This will be described with reference to FIGS. First, for example, an n ₊ diffusion layer 22 is provided on the surface of a P-type silicon substrate 21 by ion implantation, and then a high temperature CVD silicon oxide film 23 (for example, a high temperature CVD silicon oxide film 23 to be a first dielectric film is formed at a temperature of 700 ° C. or higher (for example Thickness 200
Å) is deposited (see FIG. 2 (a)).

Then, a polycrystalline silicon film (for example, with a thickness of 2000
Å) is deposited and patterned to form a first-layer conductor film 24, and then a second-layer high temperature CVD silicon oxide film 25 is deposited (see FIG. 2B).

Then, the high temperature CVD silicon oxide of the portion 26 is formed so that the second conductive film can be electrically connected to the n ₊ diffusion layer and is not electrically connected to the first conductive film 24. After selectively removing the film and exposing a part of the n ₊ diffusion layer 22, a polycrystalline silicon film is deposited and patterned to form a conductor film 27 (see FIG. 2C).

Thereafter, after depositing the high temperature CVD silicon oxide film 28, the third-layer conductor film 29 is electrically connected to the first-layer conductor film 24 (see FIG. 2D), and the fourth The capacitor film according to the present invention is formed by alternately forming a polycrystalline silicon film and a high temperature CVD silicon oxide film so that the conductor film of the second layer is electrically connected to the conductor film 27 of the second layer. Can be manufactured. In this example, the layers were stacked while electrically connecting the conductor films of the respective layers, but when stacking the layers, only patterning of the conductor films was performed, and finally, all the conductor films were stacked. It can also be electrically connected. Further, the high temperature CVD silicon oxide film and the polycrystalline silicon film have been described as an example, but as the CVD insulating film, a silicon nitride film and an oxynitride film formed by the CVD method may be used as the conductor film. A high melting point metal or a silicide thereof can be used.

FIG. 3 is a sectional view of an embodiment in which the semiconductor integrated circuit capacitor of the present invention is used in a memory cell of a dynamic RAM. In FIG. 3, 31 is, for example, a P-type silicon substrate, 32
Is an oxide film in the element isolation region. Reference numerals 33, 34 and 35 respectively denote the gate electrode of the MOS transistor and two n ₊ diffusion layers, which are electrically connected to the word line 36, the bit line and the electrode 38 of the capacitor 37, respectively. The memory cell of such a dynamic RAM can be highly integrated and have excellent memory retention characteristics because the area occupied by the capacitor can be reduced and only the capacitance can be increased.

〔effect〕

As described above, according to the present invention, since the high temperature CVD silicon oxide film formed at a temperature of 700 ° C. or higher is used as the dielectric film, the dielectric strength is high even if the dielectric film or the conductor film is thinned. It is possible to obtain a capacitor for a semiconductor integrated circuit having a multi-layer structure with a small occupying area and a large electrostatic capacity, and because it has a small thickness, it can be realized without causing breakage of Al wiring or the like passing over it. Therefore, if the semiconductor integrated circuit capacitor according to the present invention is used for a memory cell of a dynamic RAM or the like, high integration can be achieved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit capacitor according to the present invention, and FIGS. 2A to 2D are cross-sectional views in order of steps of a method for manufacturing a semiconductor integrated circuit capacitor according to the present invention.
FIG. 1 is a sectional view of a memory cell of a dynamic RAM to which the semiconductor integrated circuit capacitor according to the present invention is applied.

 ─────────────────────────────────────────────────── --Continued from the front page Judgment panel for referees Chief referee Masaaki Endo Judge Tsuneya Sekine Judge Kawai Akira (56) References JP 59-104156 (JP, A) JP 59-188963 (JP, A) ) JP-A-60-9154 (JP, A) JP-A-58-61660 (JP, A) JP-A-56-142642 (JP, A) Kazuo Maeda, "Latest LSI Process Technology" (SHO-58-7- 25) Industrial Research Board 211 ~ 229

Claims (1)

[Claims] 1. A capacitor for a semiconductor integrated circuit having a multi-layer structure in which conductor films and dielectric films formed on a semiconductor substrate are alternately stacked, wherein the conductor film is a polysilicon film or a refractory metal film. And a silicide film, wherein the dielectric film is a high temperature CVD silicon oxide film having a film thickness of 200 Å or less formed at a temperature of 700 ° C. or more.