JPH0770966B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that removes an offset signal.

[Outline of Invention]

According to the present invention, in a semiconductor integrated circuit for removing an offset signal superimposed on an analog arithmetic circuit, an input signal of the analog arithmetic circuit and an output signal of an integrating circuit which is an estimated value of the offset signal are supplied to independent input circuits of the analog arithmetic circuit. By doing so, a semiconductor integrated circuit having a small circuit scale and stable circuit characteristics is realized.

[Conventional technology]

In recent years, along with the rapid progress of semiconductor integrated circuit technology, various analog arithmetic circuits that have conventionally been composed of individual parts such as resistors and capacitors have been used for the purpose of downsizing, cost efficiency and reliability improvement of the device. Integration is being actively carried out.

However, in the integration of such an analog arithmetic circuit, due to the offset signal superimposed on the output of the arithmetic circuit,
Degradation of the circuit accuracy may be a problem, and as a circuit to remove such offset signal efficiently,
There is a circuit described in Proceedings of the Annual Conference of IEICE General Conference No. 498.

FIG. 2 shows a conventional integrated offset removing circuit. In the circuit shown in the figure, a switched capacitor integrating circuit composed of an operational amplifier A4, capacitors B6, B7, and analog switches (hereinafter, switches) S14, S15, S16, S17 is an operational amplifier A3, capacitors B8, B9. And the output Y0 of the analog operation circuit
To output the estimated value S of the offset signal to be superimposed, and subtract the estimated value S from the analog input signal Yi in the input circuit (capacitance B8 and switches S18, S19, S20, S21) of the arithmetic circuit. The output terminal OUT of the arithmetic circuit
The offset signal in is removed.

Here, the transfer function of the discrete time system of the circuit shown in FIG. 2 H _{1
(Z) (Z = e sT} , S = jw, T is the sampling period) if, H ₁ (Z) can be shown by the general formula (1).

In the formula (1), Ci (i = 6 to 9) is the capacitance value of the capacitance Bi, and when ωT << 1, the formula (1) becomes (2)
It can be approximated as a transfer function H ₁ (S) of a continuous time system shown in the equation.

As is clear from the equation (2), the transfer function of the circuit shown in FIG. 2 is equivalent to that of the first-order high-pass filter, and the output terminal
The offset signal (w0) at OUT is removed.

[Problems to be Solved by the Invention] However, in the conventional offset removing circuit shown in FIG.
As described in the above-mentioned paper, due to the influence of the parasitic capacitance C _P shown in the figure, the transfer relationship in the case of actual integration is as shown in the equations (3) and (4).

and Here, H ′ (Z) is a transfer function of a discrete time system when integrated, H ′ ₁ (S) is a transfer function of a continuous time system, and α ′ ₁ and β ′ ₁ are ,Each Therefore, the characteristics fluctuate. This parasitic capacitance is mainly
The depletion layer capacitance in the drain diffusion of the analog switch and the oxide film insulation capacitance. In particular, since the depletion layer capacitance changes with the power supply voltage and the ambient temperature, the circuit characteristics also depend on the power supply voltage and the ambient temperature. However, it was not possible to stably obtain highly accurate circuit characteristics.

Further, in the circuit of FIG. 2, it is necessary to sufficiently increase the time constant τ ₁ in the transfer function of the expression (2) with respect to the frequency band of the input signal Yi.

The time constant of the equation (2) is represented by the equation (5), Cannot be set arbitrarily because it is a variable indicating the voltage gain of the analog arithmetic circuit, and must normally be treated as a default value.

Therefore, in order that the characteristics of the offset removal circuit do not affect the frequency band of Yi, the estimated value S of the offset signal S
The capacity ratio C7 / C6 of the output integrating circuit must be made sufficiently large, and when integrated, the capacity ratio becomes large and the circuit scale increases.

The present invention is intended to improve such a problem. An object of the present invention is to eliminate an offset signal superimposed on an output of an analog arithmetic circuit, to be stable without being influenced by a parasitic capacitance, and to have a small circuit scale. To provide a semiconductor integrated circuit and a setting means of a time constant (hereinafter, referred to as “offset removal time constant”) as a circuit for removing an offset, which is optimum for highly integrating the semiconductor integrated circuit. is there.

[Means for solving problems]

A semiconductor integrated circuit of the present invention includes a first input circuit including a switched capacitor circuit having a first sampling capacitor element and a second input circuit including a switched capacitor circuit having an output of an integrating circuit as an input and having a second sampling capacitor element. An input circuit, a first operational amplifier that inputs an output of the first input circuit and an output of the second input circuit to perform analog operation, one input terminal of the first operational amplifier and the first operation amplifier An analog operational circuit including a first integrating capacitive element connected to the output terminal of the operational amplifier, and a switched capacitor circuit having an output of the analog operational circuit as an input and having a third sampling capacitive element;
Of the second operational amplifier, and a second integrating capacitance element connected between the one input terminal of the second operational amplifier and the output terminal of the second operational amplifier, and integrates the output of the analog operational circuit. And a capacitance ratio between the second sampling capacitance element and the first integration capacitance element of the analog calculation circuit, the third sampling capacitance element of the integration circuit, and It is characterized by having an offset removal time constant based on the product of the capacitance ratio with the second integrating capacitive element.

[Action]

According to the above configuration of the present invention, it is possible to remove the offset signal superimposed on the output of the analog operation circuit only by the switched capacitor circuit which is insensitive to the parasitic capacitance. Also, by supplying the output signal of the integration circuit, which is the estimated value of the offset signal superimposed on the output of the analog arithmetic circuit, to the input circuit independent of the input circuit to which the input terminal of the analog arithmetic circuit is connected, Since the time constant can be realized by the product of the capacitance ratio of the analog operation circuit and the capacitance ratio of the integration circuit, the semiconductor integrated circuit has a small circuit scale.

〔Example〕

FIG. 1 (a) is a circuit diagram showing an embodiment of the present invention.
FIG. 2B is a diagram showing the operation timing of each switch in FIG. 1A, and will be described in detail below.

First, the timing clocks φ _A and φ _B shown in FIG.
Is a two-phase clock that does not overlap with each other.
Each switch in FIG. 1A becomes N (conductive state) at the timing of "ON" shown in FIG.

The circuit shown in FIG. 1 (a) has a capacitance B1, a switch S1,
A first input circuit composed of S2, S3, S4 and connected to the input terminal IN and a capacitor B2, and a switch S5, S6, S7, S8, an operational amplifier A2, capacitors B4, B5, and a switch. S9, S10,
An analog arithmetic circuit comprising a second input circuit connected to the output terminal of an operational amplifier A2 which is the output of a switched capacitor integrating circuit composed of S11 and S12, an operational amplifier A1, a capacitor B3 and a switch S13, It shows a case where the output terminal OUT is connected to S11 which is an input switch of the integrating circuit.

Now, the circuit shown in FIG. 1 (a) is changed to the time shown in FIG. 1 (b).
If t ₁ (clock φ _B is N), then switch S
When S1 and S4 become N, the sampling capacitor B1 is charged with the input signal voltage Yi (t1) at time t1 as the input signal charge C1 · Yi (t1). (Where C1 is capacity B1
At the same time, the switches S6 and S8 are turned N, so that the output voltage S (t1) of the operational amplifier A2, which holds the integrated value of the analog operation circuit output Y0 before t = t1, is offset to the sampling capacity B2. It is charged as the estimated charge C2 · S (t1). (Here, C2 is the capacitance value of the capacitance B2.) Furthermore, by the switches S13, S10, S12 being N,
All the charges charged before t = t1 of the capacitors B3 and B5 are discharged.

Next, at time t2 in FIG. 1 (b), the switches S1, S4, S6, S
8, S13 is OFF (non-conducting state), switches S2, S3, and switches S5, S7 are N, so that at t = t1, all the charges charged in sampling capacitors B1 and B2 are transferred to capacitor B3. Then, the output voltage of the operational amplifier A1 which is the output of the analog operation circuit becomes Y0 (t2). Further, since the switches S10 and S12 are FF and the switches S9 and S11 are N, the output Y0 (t2) of the analog operation circuit is stored in the capacitor B5 and the charge C5.
-Charged as Y0 (t2).

Therefore, paying attention to the output voltage Y0 (k _n T) of the analog operation circuit at t = k _n T (k is an arbitrary integer),
The transfer functions H0 (Z) and H0 (S) in the discrete-time system and the continuous-time system of the circuit shown in FIG.
Equation (7) is shown.

(here, As is apparent from the equations (6) and (7), the voltage gain constant of the analog arithmetic circuit is , The time constant τ ₀ (= T / β
₀ ) is given by the equation (8).

Therefore, according to the equation (8), the time constant τ ₀ of the offset removing circuit according to the semiconductor integrated circuit of the present invention is calculated as follows: the capacitance ratio (C2 / C3) between the capacitances B3 and B2 of the analog arithmetic circuit and the capacitance B of the integrating circuit.
Since it depends only on the product of the capacitance ratio (C5 / C4) of 4, B5 and not on the parasitic capacitance at all, the circuit scale can be greatly reduced compared to the past by appropriately selecting the capacitance ratio in each circuit. It is possible to obtain stable circuit characteristics independent of the power supply voltage and the ambient temperature.

〔The invention's effect〕

As described above, according to the present invention, since there is no influence of the parasitic capacitance, it is possible to obtain stable circuit characteristics that do not depend on the power supply voltage or the ambient temperature.

Furthermore, when the same transfer function is realized as compared with the conventional circuit, the time constant as the offset removal circuit is determined by the product of the capacitance ratio of the analog operation circuit and the capacitance ratio of the integration circuit, and therefore the total capacitance value It is possible to reduce the circuit scale such as a large reduction (the same reference capacitance value), which is effective for high integration.

In the embodiment of the present invention, the case of the simplest amplification circuit is described as the analog arithmetic circuit, but an analog arithmetic circuit that realizes an arbitrary transfer function is used without departing from the spirit of the present invention. You can

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram showing an embodiment of an integrated offset removing circuit by a semiconductor integrated circuit of the present invention. FIG. 1 (b) is an operation timing chart of each switch in FIG. 1 (a). FIG. 2 is a circuit diagram showing a conventional example of an integrated offset removing circuit. IN …… Signal input terminal OUT …… Signal output terminal A1 to A4 …… Operational amplifier S1 to S22 …… Switch B1 to B9 …… Capacitance element φ _A , φ _B …… Clock

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masao Shindo Inventor Masao Shindo 3-5 Yamato 3-chome, Suwa City, Nagano Stock Company Suwa Seikosha Co., Ltd. (56) Reference JP-A-55-38796 (JP, A) Sho 61-196612 (JP, A)

Claims (1)

[Claims] 1. A first input circuit comprising a switched capacitor circuit having a first sampling capacitance element, and a second input circuit comprising a switched capacitor circuit having an output of an integrating circuit as an input and having a second sampling capacitance element,
A first operational amplifier that inputs an output of the first input circuit and an output of the second input circuit to perform analog operation, one input terminal of the first operational amplifier, and the first operational amplifier An analog arithmetic circuit composed of a first integrating capacitance element connected to the output terminal of the switch, and a switched capacitor circuit having an output of the analog arithmetic circuit as an input and having a third sampling capacitance element;
Of the second operational amplifier, and a second integrating capacitance element connected between the one input terminal of the second operational amplifier and the output terminal of the second operational amplifier, and integrates the output of the analog operational circuit. And a capacitance ratio between the second sampling capacitance element and the first integration capacitance element of the analog calculation circuit, the third sampling capacitance element of the integration circuit, and A semiconductor integrated circuit having an offset removal time constant based on a product of a capacitance ratio with a second integration capacitive element.