JPH0770993B2 - Digital loop filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] For a carrier wave regenerating circuit for regenerating a carrier wave for receiving, detecting and demodulating a transmission wave in which data is digitally modulated, for example, 4-phase PSK modulation, as an output of a voltage controlled oscillator VCO. PLL
Of the digital loop filter, the output value C of the up / down counter 1 serving as a loop filter that integrates the detection error of the phase detector of the PLL and the correction value ΔF provided for canceling the error are When the output value A of the adder 3 added by selecting addition / subtraction by the delay advance Φ becomes large and the overflow exceeds the predetermined upper limit value on the positive side by chance and the underflow exceeds the lower limit value on the negative side, For the purpose of preventing the PLL from getting out of sync and out of sync,
A detection unit (4) for detecting the overflow or underflow by the MSB bit that is one bit higher than the predetermined bit of the detection error and the output of the adder 3, and the output d2 of the detection unit of the counter 1. At the same time as stopping the counting operation, instead of the data A of the predetermined number of bits of the output of the adder 3, the output d1 having all of the predetermined number of bits of the logical value H or the logical value L is selected (5) to control the voltage. It is configured to output to the oscillator.

[Industrial application field]

The present invention is directed to a demodulator for receiving a quadrature detection of a transmission wave obtained by digitally modulating, for example, four-phase PSK modulation of a carrier of one radio frequency on the transmission side on the reception side and restoring the data on the transmission side. The present invention relates to a digital loop filter of a phase-locked loop PLL such as for a carrier recovery circuit that reproduces a carrier required for detection as an output of a voltage controlled oscillator, and the received signal is output by the output of the voltage controlled oscillator VCO of the PLL. The phase error of the output of the phase detector that detects the phase difference from the output phase of the voltage controlled oscillator VCO with the phase of the quadrature detected and demodulated data as a reference is digitally integrated to When the output value of the digital loop filter used as the DC DC control voltage increases by accident and exceeds the upper limit on the specified positive side, or when it exceeds the lower limit on the negative side. During that underflow,
It is an object of the present invention to provide a digital loop filter capable of automatically preventing the PLL from getting out of synchronization by being out of synchronization with a pull-in state.

[Conventional technology]

FIG. 3 shows the configuration of a conventional PLL digital loop filter for a carrier recovery circuit for demodulating a 4-layer PSK modulated signal wave or the like.

The phase detector 10A for detecting the phase difference of the output of the voltage controlled oscillator 20A based on the phase of the data obtained by orthogonally detecting and demodulating the received signal by the output of the voltage controlled oscillator 20A of the PLL (not shown in the whole) is , The sign Φ of the phase error of the output deviating from the reference phase (L), the lead (H) is input to the up / down counter 1A, and the up / down counter 1A receives the phase delay error of the code Φ. The input clock CLK is counted up by the logical value L of and the input clock CLK is counted down by the logical value H of the phase advance error of the code Φ, thereby integrating the phase lag advanced error of the output of the phase detector 10A A count value C corresponding to the DC DC output voltage is output.

The adder / subtractor selector 2A uses the sign Φ (a signal representing positive or negative polarity) of the delay (L) or advance (H) of the phase error of the output of the phase detector 10A as a selection signal SEL, and the error is generated in an external ΔF circuit. For example, it is selected whether to add or subtract a non-polarity correction value ΔF of 12 bits, which is set and given for canceling, and adds a polarity bit MSB at the time of addition and adds 13 bits of ΔF.
Output the value (however, the 13th bit of MSB is "0"),
When subtracting, the 13-bit Δ with the polarity bit MSB
The inverted value of the sign 1/0 of the F value is output. In addition, the up / down counter 1A also selects the ΔF value when counting up
Only the F value is counted up, the total is 13 bits, and the MSB is 13
A 12-bit count value C with the bit set to "0" is output, and at the time of countdown, similarly, the entire 13-bit inverted value of ΔF is selected and counted down.

The adder 3A sets 13 bits of the count value C for which the 13-bit MSB from the up / down counter 1A is “0” and the 13-bit MSB from the addition / subtraction selector 2A is “0”.
13-bit addition with the bit correction value ΔF or ΔF inverted value is performed, and the lower 12 bits of the 13-bit addition value A are used as the predetermined 12-bit control signal for the voltage-controlled oscillator.
Output to 20A. The addition of the inverted value of ΔF to the count value C by the adder 3A means the subtraction of the ΔF value from the count value C.

[Problems to be solved by the invention]

The digital loop filter of the PLL for the conventional carrier recovery circuit shown in FIG. 3 has the phase detector 10A as described above.
For example, a 12-bit correction value ΔF given from an external ΔF circuit for canceling the detection error of
13-bit adder by selecting whether to add or subtract at 2A
At 3A, the output value of the up / down counter 1A is added to or subtracted from the count value C, and the lower 12 bits of the lower 13 bits of the resulting output value are used as the predetermined 12-bit control signal A for the voltage controlled oscillator. Outputs to 20A. Therefore, the phase error of the output of the phase detector 10A fluctuates above and below any fixed value between the positive upper limit value and the negative lower limit value of the PLL control range, and ΔF is added. When an output value of the adder 3A exceeds a predetermined upper limit value with a certain probability or an underflow exceeding a predetermined lower limit value occurs by subtracting ΔF, a voltage controlled oscillator is generated.
The predetermined 12-bit output value A to 20A sharply drops or rises, and the oscillation frequency of the voltage controlled oscillator 20A drastically changes. Therefore, the up / down counter in Fig. 3
1A, adder / subtractor selector 2A, adder 3A
Loop filter, voltage controlled oscillator 20A and phase detector 10A
There is a problem that the PLL loop composed of and is out of synchronization because it is out of the synchronization state in which it is pulled to a value in a certain range in synchronization with the input data.

FIG. 4 is an explanatory diagram for explaining the problems of the conventional digital loop filter, in which the vertical axis is the output value of the adder 3A which is the integral output of the loop filter, and the phase detector
It represents the added value of the counter value C of the output of the up / down counter 1A that integrates the phase error of the output of 10A and the correction value ΔF given from the outside for canceling the detection error.

The added value is usually 0V (12-bit code 1000 0000 00
Centered around 00), positive limit value 127V (12-bit code 1111
1111 1111) and negative limit value -128V (12-bit code 0000
Although it is distributed above and below any constant value between 0000 0000), it overflows beyond the upper limit value 127V on the positive side, that is, the counter value C (1111 1111 1111) and the correction value Δ, for example.
When the added value obtained by adding F (0000,0000,0011) becomes (13-bit code 1 0000 0000 0011) as shown in the figure, the predetermined 12-bit output A of the adder 3A is called (0000 0000 0011). Is output as a value and the predetermined 12-bit output A is (1111 1
It changes rapidly from (111 1111) to (0000 0000 0011).
Also, the phase error of the output of the phase detector 10A becomes large on the negative side, the counter value C of the counter 1A becomes small, and it underflows beyond the lower limit value -128V on the negative side, that is, the counter value C (0000 0000 0000) to the correction value ΔF (0000,0000,001
1) is subtracted, that is, the addition value obtained by adding the counter value C and the inverted value (1111, 1111, 1100) of the correction value ΔF is (11
11 1111 1110), the predetermined 12-bit output A of the adder 3A suddenly changes from (0000 0000 0000) to (1111 1111 1110), and the polarity of the output A also changes from negative to positive.

That is, the phase error of the output of the phase detector 10A largely fluctuates due to some cause of the reception input, and the output value of the adder 3A becomes
When an overflow or underflow accidentally exceeds a predetermined upper or lower limit value, a predetermined 12-bit output A to the voltage controlled oscillator 20A suddenly drops or rises, and the oscillation frequency of the voltage controlled oscillator 20A. Suddenly changes, and normal control of the PLL becomes impossible.

[Means for solving problems]

The problem with this conventional example is that the counter value C, which is the output of the adder 3 of the output of the digital loop filter, and the correction value ΔF.
The normal logical value of the MSB bit (D13), which is one bit higher than the predetermined bit A (12 bits in the conventional example) of the addition value of
When "L" overflows by adding ΔF at the upper limit value on the positive side, it becomes logical value 1 "H", and at the lower limit value on the negative side ΔF.
When subtracting and underflowing, the polarity of the output value of the adder 3 changes and the normal logical value "L" of the MSB bit (D13)
Paying attention to the fact that the logical value becomes “H”, referring to the principle diagram showing the basic configuration of the present invention in FIG. 1, the MSB one bit above the predetermined output A (12 bits) of the adder 3 Bit (D13)
And the lag lead code Φ of the phase error of the output of the phase detector 10.
And PLL sweep / track status signal S (in the sweep state, the control voltage of the voltage controlled oscillator is repeatedly swept from the lower limit value to the upper limit value of normal control in order to pull the PLL from the out-of-sync state to the synchronized state. The out-of-track condition is the track condition, in which the PLL is normally controlled so as to cancel the phase error that occurs above and below the fixed value within the limit value after pulling the PLL into the sync condition. The sweep state is designated by, for example, a logical value L, and the track state is designated by a logical value H), and gate processing is performed. A detector (4) that detects an overflowing overflow or an underflow that exceeds the lower limit value on the negative side and the detection signal (d2) stop the counting operation of the counter 1 and at the same time the predetermined number of bits of the adder 3 Instead of output A , An output selector (5) for selecting a signal (d1) having all of the predetermined number of bits as a logical value H or a logical value L. The output selector (5) is used as an output, and the adder 3 is normally provided. Output A of specified number of bits of
Is output, and a signal (d1) having all bits of a predetermined number of bits as a logical value H or a logical value L is output to the voltage controlled oscillator 20 as a control signal at the time of overflow or underflow. It That is, the counter 1 stops its counting operation by the detection signal d2 of the detection unit (4), and the output selector (5) activates its selection operation, instead of the predetermined output A of the adder 3. A signal d1 in which the logical value H / L of the detection signal d1 of the detection unit (4) is selected and all bits of the output bits of a predetermined number of bits are set to the logical value H or the logical value L
Is output to the voltage controlled oscillator 20 as a control signal at the time of overflow or underflow.

[Action]

The counter 1 counts up the input clock CLK at the time of phase delay according to the logical value L / H of the delay lead code Φ of the phase error from the phase detector 10 of the phase locked loop PLL,
When the phase advances, it counts down and outputs the count value C of the count result to the adder 3.

The addition / subtraction selector 2 performs addition / subtraction of the phase error of the output of the phase detector 10 and a correction value ΔF given for canceling the error from the outside, and advances the phase error of the output of the phase detector 10. The signal Φ representing the delay, that is, the positive / negative polarity is selected
And outputs the ΔF value to the adder 3 during addition,
At the time of subtraction, the inverted value of the sign H / L of the ΔF value is output to the adder 3.

The adder 3 adds the count value C of the output of the counter 1 and the ΔF value or the inverted value of ΔF of the output of the addition / subtraction selector 2 and removes the MSB representing the positive / negative polarity of the added value by a predetermined number of bits (for example, 12 Bit A) data A is output to the output selector 4, and the MS one bit higher than the predetermined bit A (12 bits)
The B bit (D13) is output to the detection unit 4.

The detection unit 4 inputs the MSB bit (D13) of the output of the adder 3, the delay lead code Φ of the phase error of the output of the phase detector 10, and the sweep / track state signal S to perform gate processing, In the track state in which the PLL is synchronized with the phase of the input data, the output of the adder 3 accidentally detects an overflow exceeding a predetermined positive upper limit value or an underflow exceeding a negative lower limit value, and detects a detection signal d (d1 , d2) is output.

The output selector 5 is activated by the output signal d2 of the detection unit 4, and instead of the predetermined output data A of the adder 3 of the output of the counter 1 stopped by the output signal d2, the detection unit 4
H / L of the output signal d1 is output to the voltage controlled oscillator 20 as a signal d1 in which all of the predetermined number of bits of the output A have the logical value H or the logical value L.

The digital loop filter of the present invention has a counter value C of the output of the counter 1 which is the integrated value of the positive and negative detection error of the output of the adder 3, that is, the output of the phase detector 10, and an external value for canceling the error. When the added value A of the sum or difference with the given correction value ΔF overflows or underflows beyond the predetermined upper or lower limit value, it is detected by the phase detector 10
Of the detection error of the output of the output of Φ and the MS of 1 bit higher than the predetermined bit A (12 bits) of the output of the adder 3
Depending on the logical value H of the B bit (D13), the overflow or underflow detection signal d (d1, d
2) stops the operation of the counter 1 and outputs the output selector 5
The above operation is started, and the output from the output selector 5 to the voltage controlled oscillator 20 is output as “all H” or “all L” that sets all of a predetermined number of bits to H or L. Therefore, when the output of the adder 3 overflows or underflows, the output value as the control signal to the voltage controlled oscillator 20 in the next stage does not change abruptly.
The oscillating frequency is gradually controlled. Therefore, the PLL constituted by the digital loop filter of the present invention, the voltage controlled oscillator 20 and the phase detector 10 is prevented from being out of synchronization due to an overflow or an underflow which occurs accidentally in the synchronized state, and the problem is solved. It

〔Example〕

FIG. 2 is a block diagram showing the configuration of the digital loop filter according to the embodiment of the present invention. In FIG. 2, the counter 1 comprises an up-down counter 11 and a PLL.
Of the phase error of the output of the phase detector 10 is started by, for example, the logical value L at the time of the phase delay of the phase advance code Φ and the logical value H at the time of the phase advance, and is counted up by the input clock CLK at the time of the phase delay. At the time of advancing, the count value C is counted down by the input clock CLK, and the resulting count value C, for example, a 12-bit code is output to the adder 3. However, the MSB, which is one bit higher, is output as 13 bits with "L".

The adder / subtractor selector 2 is composed of a 12-bit selector 21 and has a correction value ΔF given from an external ΔF circuit in order to cancel the 12-bit phase error of the output of the phase detector 10 of the PLL.
Is input and a signal Φ representing the lead or lag of the phase error of the output of the phase detector 10, that is, positive or negative, is used as a selection signal SEL, and whether the ΔF is added or subtracted is selected.
The 13-bit ΔF value with the B bit set to “L” is output to the adder 3, and the inverted value of 13-bit ΔF is also output to the adder 3 during subtraction.

The adder 3 is composed of a 13-bit adder 31, and normally the contents from the counter 1 are all 13-bit MSB "L" contents 1
The 2-bit count value C is added to the 12-bit error correction value ΔF or ΔF inverted value in which the MSB of 13 bits as a whole from the addition / subtraction selector 2 is added, and the addition result of 13 bits is added. The output value A of the lower 12-bit contents is output to the output selector 4 as the output of a predetermined bit, but the output error of the phase detector 10 changes up and down in the vicinity of the upper limit value on the positive side, and the count value of the counter 11 When C becomes large and the output A of the adder 3 to which ΔF is added becomes large and overflows by accidentally exceeding the predetermined positive limit value of 12 bits, 13 bits higher than the predetermined 12 bits of output A by 13 Bit MS
The logical value "L" of D13 of B changes to "H". Also, the output error of the phase detector 10 changes in the vicinity of the lower limit value on the negative side, the count value C of the counter 11 becomes smaller, and the subtraction of the error correction value ΔF causes the output A of the adder 3 to reach the lower limit value on the negative side. When the value of the output A suddenly exceeds the value and causes an underflow in which the polarity of the output A suddenly changes from negative to positive, the logical value "L" of D13 of the MSB indicating the negative polarity of the output changes to "H". . The adder 3 outputs
The MSB D13 is output to the detection unit 4 which detects overflow / underflow.

The detection unit 4 is composed of an inverter 41, an AND gate 42, an EX-OR gate 43, an AND gate 44, and an inverter 45. The AND gate 42, EX-OR gate 43 is one of the predetermined outputs A of the adder 3.
MSB bit D13, which is 1 bit higher than 2 bits, and the inverter 41 with the lag lead code Φ of the phase error of the output of the phase detector 10.
The inverted signal is input to perform gate processing, and the output signal d1 of the processed output of the AND gate 42 is input to the output selector 5 in parallel with the normal 12-bit output A from the adder 31. The output of EX-OR gate 43 is AND gate 44.
Is externally inputted to the PLL sweep / track status signal S (the logical value L is taken during the sweep and the logical value H is taken during the track), and the output signal d2 of the ANDed output is Up-down counter 11 EN
It is input to the ABLE terminal and the select signal terminal of the output selector 5.

The AND gate 44 of the detector 4 delays the phase error between the MSB bit D13 of the output of the adder 3 and the phase error of the output of the phase detector 10 in the track state where the sweep / track state signal S takes the logical value H. EX with lead sign Φ and the inverted value
-The output of OR43 detects the overflow when the up / down counter 11 counts up, and the underflow when the countdown occurs. Also, AND gate at that time
The output signal d2 of the processing output of 44, that is, the detection signal d2 stops the counting operation of the up / down counter 11, and holds the count value at the time of overflow or underflow. At the same time, the detection signal d2 activates the output selector 5.

The output selector 5 is composed of a 12-bit selector 51,
At the time of overflow, it is activated by the detection signal d2 and selects H of the output signal d1 of the AND gate 42 to output a predetermined output.
All the 12 bits are set to logical values H, and at the time of underflow, L of the output signal d1 is selected by the detection signal d2 'which is the sign of the detection signal d2 inverted by the inverter 45, and all bits are set to the logical value L to perform voltage control. Output to oscillator 20.

The 12-bit selector 51 of the output selector 5 is normally 12 or the sum of the difference between the output value A of the adder 31, that is, the count value C of the counter 11 and the correction value ΔF for canceling the phase error of the output of the phase detector 10. The output value A of the bit is output to the voltage controlled oscillator 20 of the next stage according to the L / H of the lag lead code Φ of the phase error of the output of the phase detector 10, but the output value A is a predetermined limit value. When it overflows or underflows beyond, the operation of the counter 11 is stopped at the same time by the output signal d2 of the AND gate 44 of the detection unit 4 which receives H of D13 of MSB of the output A of the 13-bit adder 31 as an input. Output selector 51
Is activated to select H of the output signal d1 of the AND gate 42, and all bits of 12 bits of a predetermined output are set to logical value H'all H ', or all bits are set to logical value L'all L'. '
And Therefore, the output value to the voltage controlled oscillator 20 in the next stage does not change suddenly, and the oscillation frequency of the voltage controlled oscillator 20 is gradually controlled. Therefore, the digital loop filter and voltage controlled oscillator 20 of the embodiment of the present invention
The PLL composed of the phase detector 10 and the phase detector 10, even if overflow or underflow occurs even in the synchronous state,
It prevents out of sync.

〔The invention's effect〕

As described above, according to the present invention, for example, a digital loop filter forming a PLL for a carrier recovery circuit for a demodulator for receiving a 4-phase PSK modulated wave, performing quadrature detection, and demodulating transmission data is provided. In the PLL synchronization state, the output error of the phase detector changes due to fluctuations in the received input wave, etc., causing the specified output to the voltage-controlled oscillator to overflow or underflow beyond the specified limit value. Also,
At that time, the counter that integrates the detection error stops operating, and instead, the predetermined output to the voltage controlled oscillator is changed to “all H” for the positive limit value or “all L” for the negative limit value. Is output as an output, the oscillation frequency of the voltage-controlled oscillator is gradually controlled, and it is possible to prevent the PLL in the synchronous state from becoming out of synchronization, which cannot be controlled due to overflow or underflow as in the conventional case. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a configuration of a digital loop filter of the present invention. FIG. 2 is a block diagram showing a configuration of a digital loop filter of an embodiment of the present invention. FIG. 3 is a block of a conventional digital loop filter. FIG. 4 is an explanatory diagram for explaining problems in the operation of the conventional example. In the figure, 1 is a counter, 11 is an up / down counter, 2 is an adder / subtractor selector, 3 is an adder, 4 is a detector, and 5 is An output selector, 10 is a phase detector, and 20 is a voltage controlled oscillator.

Claims (1)

[Claims] 1. A lag / lead code (Φ) of a phase error from a phase detector (10) for detecting a phase difference from an output phase of a voltage controlled oscillator (20) with reference to a phase of input data,
The input clock (CLK) is counted up or down by the counter (1) and its detection error is integrated, and a count value (C) and a correction value (ΔF) given from the outside to cancel the detection error are added to the phase error. Delay lead code (Φ)
A predetermined bit of the output value (A) obtained by adding the correction value (ΔF value or ΔF inverted value) after selecting (2) whether to add or subtract as the selection signal (SEL) by the adder (3) The number (for example, 12 bits) of data is transferred to the voltage controlled oscillator (20).
Output to the phase detector (10) output phase error (Φ)
In the digital loop filter of the PLL that controls the output phase of the voltage controlled oscillator so that
Is synchronized with the input data and is pulled to a value within a certain range, the MSB bit (D13) one bit higher than the predetermined bit (12 bits) of the output of the adder (3) and the phase detector (10 ) Output of the phase error with the delay lead code (Φ) is gated to detect an overflow in which the output value (A) of the adder (3) exceeds a predetermined upper limit value or an underflow which exceeds a lower limit value. The detection unit (4) and the counter (1) based on the detection signal (d2) of the detection unit (4)
The output of the output of the adder (3) is replaced with the data (A) of the predetermined number of bits and all of the predetermined number of bits (12 bits) are set to the logical value H or the logical value L at the same time when the counting operation is stopped. A digital loop filter comprising an output selector (5) for selecting (d1) and outputting to the voltage controlled oscillator (20).