JPH0771000B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention is used in a PLL circuit and includes a first divided signal obtained by dividing an external input signal and a second divided signal obtained by dividing a reference signal. The present invention relates to a semiconductor integrated circuit that compares the phases of the above and outputs a phase comparison signal.

[Conventional technology]

FIG. 3 is a conventional circuit used in a PLL circuit for comparing the phases of a first divided signal obtained by dividing an external input signal and a second divided signal obtained by dividing a reference signal and outputting a phase comparison signal. FIG. 4 is a block diagram showing a semiconductor integrated circuit (hereinafter referred to as “PLL unit”) 10 of FIG. 4, and FIG. 4 is a system diagram of a receiving portion of a television receiver. As shown in FIG. 4, the PLL circuit 11 forms a closed loop from the voltage controlled oscillator 12, the PLL unit 10 and the low pass filter 13, fixes the phase of the signal output from the voltage controlled oscillator 12, and It is synchronized with the output signal. Further, the PLL unit 10 divides the signal obtained from the voltage controlled oscillator 12 by the first division signal and the second division signal by dividing the reference signal by the division ratio instructed by the external device 20 such as a computer. The phase comparison is performed with the frequency signal and the phase comparison signal is output to the low pass filter 13. In addition, 15 is an antenna, 16 is a mixer, and 17 is an intermediate frequency amplifier.

The PLL unit 10 has six external terminals P1 to P6 as shown in FIG.
have. The comparison signal input terminal P1 is connected to the programmable divider 1, and the enable terminal P2 is connected to the data latch circuit 2.
And the shift register 3, the data input terminal P3 and the clock input terminal P4 to the shift register 3, the reference signal input terminal
P5 is connected to the programmable reference divider 5, and the phase comparison output terminal P6 is connected to the phase comparator 5.

As shown in the waveform diagram of FIG. 5, the shift register 3 is activated when the enable signal S2 input from the enable terminal P2 is H, and is synchronized with the clock signal S4 input from the clock input terminal P4. The 1-bit data signal S3 is sequentially taken in from the input terminal P3 and shifted to store the predetermined bit data D _t . This data D _t is always output to the data latch circuit 2. As shown in FIG. 5, the data D _t is data for setting the division ratio of the programmable divider 1 (hereinafter referred to as “PD data”) D1 (upper bit group) and the division ratio of the programmable reference divider 5. It is composed of setting data (hereinafter referred to as "PRD data") D2 (lower bit group).

The data latch circuit 2 latches the data D _t in synchronization with the rising (or falling) edge of the enable signal S2 input from the enable terminal P2 (which is synchronized with the falling edge in the example of FIG. 5). Then, the PR data D1 is output to the programmable divider 1, and the PRD data D2 is output to the programmable reference divider 5.

Programmable divider 1 uses PD data D1 (value is n
Based on the above), the input signal S1 input from the comparison signal input terminal P1 is divided into 1 / n and the divided signal S1 'is output to the phase comparator 4. On the other hand, the programmable reference divider 5 outputs the reference signal input from the reference signal input terminal P5 to 1 / based on the PRD data D2 (value is m).
The frequency is divided into m and the divided signal S5 'is output to the phase comparator 4.

The phase comparator 4 detects the phase difference between the frequency-divided signal S1 'and the frequency-divided signal S5' and outputs the phase comparison signal S6 to the phase comparison output terminal P6.

Thus, the PLL unit 10 divides the frequency-divided signals S1 ′ and S5 ′ obtained by dividing the input signal S1 and the reference signal S5 from the outside into 1 / n and 1 / m, respectively, based on the data signal S3. The phase difference is compared and the phase comparison signal S6 is output to the outside.

[Problems to be Solved by the Invention]

The conventional PLL unit 10 is configured as described above, and the frequency division ratios of the programmable divider 1 and the programmable reference divider 5 are collectively set.

Therefore, even when only one of the programmable divider 1 and the programmable reference divider 5 is changed in frequency, the shift register 3 stores the data D _{t including} both frequency division ratio setting data D1 and D2 as described above. Via the data latch circuit 2 via the data latch circuit 2
To the programmable divider 1 for PD data D1 and the programmable reference divider 5 for PRD data D
It must be done by transferring 2 each. Since the number of bits of the division ratio setting data D1 and D2 is long, the time for setting the division ratio setting data that does not need to be changed, that is, the data signal S3 is input to the shift register 3 in 1-bit units from the data input terminal P3. By doing so, there is a problem in that the time required to create the frequency division ratio setting that does not need to be changed is added to the shift register 3, and the time required to set the frequency division ratio becomes unnecessarily long.

Of course, if the independent external terminals P3, P4, the shift register 3, and the data latch circuit 2 are respectively provided for fetching the PD data D1 and the PRD data D2, the above problem can be avoided, but the PLL unit 10 Is extremely unrealistic in terms of the degree of integration and the cost, because the number of external terminals cannot be easily increased.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit used for a PLL circuit that can perform efficient frequency division ratio setting processing without increasing the number of external terminals. And

[Means for Solving the Problems]

A semiconductor integrated circuit according to the present invention is used in a PLL circuit, and compares the phases of a first divided signal obtained by dividing an external input signal and a second divided signal obtained by dividing a reference signal to perform phase comparison. A circuit for outputting a signal, which takes in an external data signal from a data input terminal, an external input terminal, and the data input terminal, and generates and outputs an internal data signal composed of frequency division ratio setting data and selection data. A shift register and a data output selection circuit that takes in the internal data signal and outputs the division ratio setting data as one of the first and second selection output signals based on the selection data. And a first frequency divider that takes in the external input signal from the external input terminal and divides the external input signal based on the first selection output signal to output the first divided signal. , The above criteria Uptake, based on the second selection output signal, it is constituted by a second frequency divider for outputting the second divided signal with the reference signal by dividing No..

[Action]

The data output selection circuit according to the present invention takes in an internal data signal, and based on the selection data in the internal data signal,
Since the frequency division ratio setting data is output as one of the first and second selection output signals, the frequency division ratio setting data is output from the first and second frequency dividers. , Whichever frequency division ratio is set, if the selection data includes information for identifying the first and second frequency dividers, accurately give the desired frequency divider for frequency division ratio setting. You can

〔Example〕

FIG. 1 is a block diagram showing a PLL unit 10 which is an embodiment of the present invention. As shown in the figure, a data selection circuit 6 including a control circuit 6a and a selection circuit 6b is newly provided.

The shift register 3 'in the same manner as the conventional, the enable signal S2, data signal S3 and clock signal S4 uptake, the data latch circuit 2 data D _t' a as shown in FIG. 2, and outputs.

However, the data D _t ', as shown in FIG. 2 prior art (Fifth
Unlike the data D _{t (} see the figure), it is composed of frequency division ratio setting data D0 and selection data D3. The division ratio setting data D0 is data for setting the division ratio of the programmable divider 1 or the programmable reference divider 5, and the selection data D3 is the division ratio setting data D0 of the programmable divider 1 and the programmable reference divider 5. It is 1-bit data indicating which of the division ratio setting data is used.

Data latch circuit 2 'shift register 3''takes in the data D _t' data D _t obtained from the selection data D3 in the control circuit 6a in the data selection circuit 6, the frequency division ratio setting data D0
Is output to the selection circuit 6b in the data selection circuit 6.

The control circuit 6a takes in the enable signal S2 and the selection data D3, synchronizes with the rising (falling) edge of the enable signal S2 (in the example of FIG. 2, it synchronizes with the falling edge),
The control signal SC based on the selection data D3 is output to the selection circuit 6b.

Based on the control signal SC obtained from the control circuit 6a, the selection circuit 6b receives the division ratio setting data D0 obtained from the data latch circuit 2.
Is output to only one of the programmable divider 1 and the programmable reference divider 5. Since the other configurations are the same as the conventional ones, the description thereof will be omitted.

In such a configuration, the programmable divider 1
The division ratio is set by inputting the data input signal S3 to the shift register 3 ', and setting the division ratio setting data D0 for instructing the division ratio of the programmable divider 1 and the selection data D3 for instructing the selection of the programmable divider 1. Data consisting of and
This is done by creating D _t 'in the shift register 3'. When the data D _t ′ is created in this way, the control circuit 6a
Is a control signal for instructing the transfer of the division ratio setting data D0 to the programmable divider 1 based on the selection data D3.
SC will be sent to the selection circuit 6b. As a result, the selection circuit
6b transfers the division ratio setting data D0 only to the programmable divider 1, and only the division ratio of the programmable divider 1 is changed. Further, the division ratio setting of the programmable reference divider 5 is also performed by inputting the data input signal S3 to the shift register 3 and selecting the division ratio setting data D0 and the programmable reference divider 5 for instructing the division ratio of the programmable reference divider 5. Data D _t ′ consisting of selection data D3 instructing is generated in the shift register 3 ′ in the same manner as the division ratio setting of the programmable divider 1.

Therefore, when only one of the programmable divider 1 and the programmable reference divider 5 is changed, it is not necessary to input the data for setting the other dividing ratio to the shift register 3 ', and the shift register 3'is always operated. Since the selection data D3 that needs to be input to the register 3'is only 1 bit, long bit data is input to the shift register 3'to create unnecessary division ratio setting data when setting the division ratio. Therefore, the frequency division ratio setting time can be shortened as compared with the conventional case. Moreover, the number of external terminals is the same as before,
There is no problem that the integration degree is lowered and the cost is increased.

〔The invention's effect〕

As described above, according to the present invention, the data output selection circuit takes in the internal data signal and outputs the division ratio setting data to the first and second selection outputs based on the selection data in the internal data signal. Since one of the signals is output as the selection output signal, whichever of the first and second frequency dividers the frequency division ratio setting data is,
If the selection data includes information for identifying the first and second frequency dividers, the frequency division ratio setting data can be accurately given to the desired frequency divider.

As a result, when only one of the first and second frequency dividers is set, the shift register does not need to fetch external data for setting the other frequency division ratio from the data input terminal. Therefore, the frequency division ratio setting time is shortened by that amount, which is efficient. Moreover, no new external terminals are provided in association with the formation of the data output selection circuit, and the problems associated with the addition of external terminals do not occur.

[Brief description of drawings]

1 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the shift register shown in FIG. 1, and FIG. 3 is a conventional semiconductor integrated circuit. FIG. 4 is a block diagram showing the operation of the shift register shown in FIG. 4, FIG. 4 is a system diagram of the receiving portion of the television receiver, and FIG. 5 is a waveform diagram showing the operation of the shift register shown in FIG. In the figure, 1 is a programmable divider, 2'is a data latch circuit, 3'is a shift register, 4 is a phase comparator, 5 is a programmable reference divider, 6 is a data selection circuit, P1 is a comparison signal input terminal, and P3 is a data input. It is a terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A phase comparison signal which is used in a PLL circuit and which compares the phases of a first divided signal obtained by dividing an external input signal and a second divided signal obtained by dividing a reference signal and outputs a phase comparison signal. A semiconductor integrated circuit, comprising: a data input terminal, an external input terminal, and a shift register which takes in an external data signal from the data input terminal and generates and outputs an internal data signal composed of frequency division ratio setting data and selection data. A data output selection circuit that takes in the internal data signal and outputs the division ratio setting data as one selection output signal of the first and second selection output signals based on the selection data, A first frequency divider that takes in the external input signal from the external input terminal, divides the external input signal based on the first selection output signal, and outputs the first divided signal; Take a reference signal See, based on said second selection output signal, a semiconductor integrated circuit with the reference signal by dividing and a second frequency divider for outputting the second divided signal.