JPH0831792B2 - PLL circuit - Google Patents

Description

The present invention relates to generating a data latch signal in a PLL (Phase Loched Loop) circuit with a built-in counter.

[Conventional technology]

FIG. 2 is a block diagram of a conventional PLL circuit. In the figure, (1) is an input signal applying terminal, (2) is an enable signal input terminal, (3) is a clock input terminal, (4) is a data input terminal, (5) is a reference signal input terminal,
(6) is a phase comparison signal output terminal of the phase comparator, (7) is a programmable divider, (8) is a programmable reference divider, (9) is a shift register, (1
0) is a data latch circuit, (11) is a selection circuit, (14) is a phase comparator, and (15) is a latch circuit.

Next, the operation will be described. Input signal application terminal (1)
The signal input from the programmable divider (7)
The divided frequency division signal is divided by the programmable reference divider (8), and the divided input divided signal and the signal inputted from the reference signal input terminal (5) are divided by the programmable reference divider (8). The phase is compared with this reference frequency division signal, and the phase difference is output from the phase comparison signal output terminal (6).

The division ratio of the programmable divider (7) and the programmable reference divider (8) in this circuit is the data input to the shift register (9) from the clock input terminal (3) and the data input terminal (4). It is set by reading it into the circuit (10) and further transferring it to the programmable divider (7) and the programmable reference divider (8) under the control of the enable signal input terminal (2).

[Problems to be Solved by the Invention]

Since the conventional PLL circuit is configured as above,
When setting the division ratio of the programmable divider and programmable reference divider, the data stored in the data latch circuit is controlled by the control signal input from the enable signal input terminal and the signal output from the data latch circuit. I was transferring to one of the dividers. Therefore, when transferring data from the data latch circuit, a control signal input from the enable signal input terminal is required. That is, there has been a problem that a control signal input terminal for data transfer must be provided as an external terminal.

The present invention has been made in order to solve the above problems, and is provided with a counter circuit inside the circuit, and counts the clocks input from the clock input terminal, and when a certain number of clocks are counted, An object is to obtain a PLL circuit that generates a signal similar to the control input applied to the enable signal input terminal and inputs the signal to the latch selection circuit.

[Means for solving the problem]

The PLL circuit according to the present invention is provided with a counter circuit in the circuit of FIG. 2, and the data for determining the division ratio from the data latch circuit is programmable by the latch signal of the counter circuit and the selection signal of the data latch circuit. Alternatively, it is transferred to the programmable reference divider.

[Action]

The PLL circuit according to the present invention has a built-in counter circuit and can generate a signal (latch signal) similar to the control input signal input from the enable signal input terminal of the circuit shown in FIG. It is possible to omit the enable signal input terminal of the circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PLL circuit.

In the figure, (1), (3) to (11), (14) are the second
The description is omitted because it is the same as that shown in the conventional example of the figure. (12) is a latch selection circuit, and (13) is a counter circuit. Next, the operation will be described. Counter circuits (13)
Counts the number of clocks input from the clock input terminal (3) and outputs a latch signal to the latch selection circuit (12) when the number reaches a certain number. The latch selection circuit (12) uses a latch signal from the counter circuit (13) and a signal from the data latch circuit (10) to convert the data stored in the data latch circuit (10) to a programmable divider (7) or a programmable reference divider. Transfer to either one of (8). Here, the signal output from the data latch circuit (10) to the latch selection circuit (12) is 1-bit data of "0" or "1". For example, when it is "0", the programmable divider (7) The data for setting the division ratio from the data latch circuit (10) to the programmable reference divider (8) for setting the division ratio from the data latch circuit (10). It transfers data. The selection circuit (11) receives the 1-bit data and transfers the data for setting the division ratio from the data latch circuit (10) to either one of them. The control signal (1 bit data as described above) for transferring the data for setting the division ratio is the latch selection circuit (12).
The counter circuit (13) incorporated therein needs to be reset at the time of being output from the selection circuit (11). This reset operation is performed using a control signal for data transfer.

〔The invention's effect〕

As described above, according to the present invention, the signal (latch signal, selection signal) for transferring the data for determining the division ratio from the inside of the data latch circuit to the programmable divider and the programmable reference divider is a PLL circuit. This is implemented by providing a counter circuit inside. This has the effect of reducing the number of external control signal input terminals.

[Brief description of drawings]

FIG. 1 is a block diagram showing a PLL circuit section according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional PLL circuit. In the figure, (1) is an input signal applying terminal, (3) is a clock input terminal, (4) is a data input terminal, (5) is a reference signal input terminal, (6) is a phase comparison signal output terminal,
(7) is a programmable divider, (8) is a programmable reference divider, (9) is a shift register, (10) is a data latch circuit, (11) is a selection circuit,
(12) is a latch circuit, (13) is a counter circuit, and (14) is a phase comparator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A programmable divider for dividing an input signal from the outside and outputting a first divided signal, and a programmable reference for dividing a reference input signal from the outside and outputting a second divided signal. A divider and a phase comparator which receives the first and second divided signals, compares the phase of the first divided signal with the phase of the second divided signal, and outputs the phase difference. A clock input terminal for inputting a clock from the outside, a data input terminal for inputting data from the outside, a shift register for receiving the clock and the data, and latching and dividing the data input to the shift register. A data latch circuit that outputs data for setting the ratio and data for setting the division ratio output from the data latch circuit are output based on the selection signal based on the selection signal. In a PLL circuit comprising a selectable circuit for transferring to a programmable divider or the programmable reference divider, a dividing ratio in the programmable divider and the programmable reference divider is determined based on data for setting the dividing ratio, A counter circuit that counts the number of clocks input from the clock input terminal to the shift register and outputs a latch signal when the count reaches a predetermined number; and data for setting the division ratio. Is transferred to the programmable divider or is transferred to the programmable reference divider, the selection signal is received from the data latch circuit, and the selection signal is output to the selection circuit based on the latch signal. latch And a selection circuit, wherein the selection signal is a PLL for resetting the counter circuit.
circuit.