JPH0771116B2 - Serial data receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data receiver incorporated in a microprocessor.

2. Description of the Related Art Conventionally, a serial data communication device, which has been widely used in one-touch microprocessors, is composed of a shift register, a shift counter, and a buffer register. It is shown.

In recent years, the spread of microprocessors has been remarkably used in many household electric appliances, and it is not uncommon for a VTR or the like to use several microprocessors per unit. In devices incorporating many microprocessors, serial communication is often used as a means for exchanging information between processors. As a method of transmitting information, a 4-bit or 8-bit unit frame is continuously transmitted for several blocks, and the first frame thereof includes identification data of a processor as a transmission partner, that is, identification data indicating a destination of the data. Has been. As the amount of intercommunication between processors increases and information flows back and forth on a common serial communication line, each processor must make a great deal of effort to receive data in order to receive the information accurately. Disappear.

That is, each processor starts a serial interrupt process and decodes the contents of the serial buffer every time one frame of serial data is read into the serial buffer, and the processor decodes the contents of the serial buffer. It must be judged in each serial interrupt processing routine whether or not the information is sent to the corresponding device. Therefore, as a result of collating the identification data with the comparison data unique to the processor, even if the information is sent to another processor, at least the processing until the identification data is decoded must be performed. No, it was a heavy burden. For this reason, a method has been proposed in which the identification data is recognized by hardware without receiving the serial data reception by software, but in that case, since the identification number is different for each processor, each processor is The wear circuit must have each identification number, and there is a problem that flexibility is lost in changing the identification number and setting the shared identification number.

Means for Solving the Problems In order to solve the above-mentioned problems, in a serial data receiving device of the present invention, a memory means for parallel-converting a data string supplied to a serial data input terminal and storing at least one frame. Comparing means for comparing the identification data stored in the memory means and indicating the destination of the data with unique comparison data supplied via a data bus for collating with the identification data; and the identification data by the comparison means. And an interrupt signal output means for outputting the coincidence output of the comparison data as an interrupt request signal of the microprocessor and fetching the subsequent information stored in the memory means by the interrupt processing routine of the microprocessor.

Effect In the present invention, the configuration described above makes it possible to set or change comparison data and fetch valid information by software, and the identification data is confirmed by hardware, which reduces the load on software and is highly versatile. A communication device can be realized.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention. A 4-bit constant level cyclic shift register 100 is supplied with a reception clock through a serial clock terminal 1. And a 2-bit counter 2 that counts the number of cycles of the shift register 100
00 and parallel data is the data bus 2 of the microprocessor
To the shift register 100 and the counter 200.
The data at the bit position decoded by the output of
The random access memory 300 supplied from the serial input terminal 310 and the digital comparator 400 for comparing the comparison data supplied from the data bus 2 with the data stored in the random access memory 300 constitute the main part. Also, one bit of the shift register 100 and the output of the counter 200 are supplied to the D terminal of the D flip-flop 3, the output signal of the D flip-flop 3 is supplied to the reception operation completion notification terminal 4, and AND The digital comparator 4 via the gate 5
The comparison enable terminal 401 of 00 and the AND gate 6 are supplied. The comparison output signal of the digital comparator 400 and the output signal of the AND gate 6 are supplied to the serial interrupt signal output terminal 8 via the OR gate 7. Further, the reset terminal 9 and the clear terminal 10 are connected to the non-latch type output port of the microprocessor to supply the reset signal by software, and the interrupt disable terminal 11
Is connected to the output port of the microprocessor latch type and is used for interrupt control by software. The signal supplied to the serial data input terminal 12 is configured to be applied to the serial input terminal 310 of the random access memory 300 via the Schmidt type inverter 13 and the inverter 14. Meanwhile, the timing signal generated by the timing signal generating circuit 500 from the clock signal supplied to the serial clock terminal 1 and the clock signal supplied to the system clock input terminal 15 is the serial data read clock input of the random access memory 300. It is supplied to the terminal 330. The output of the random access memory 300 is also supplied to the data bus 2 via the bus switcher 600,
A select signal for reading the parallel output of the random access memory 300 into the data bus is supplied to the block select terminal 16 connected to the bus switcher 600.
A comparison disable signal from the microprocessor is supplied to the other input terminal of the AND gate 6 via the comparison prohibiting terminal 17. Further, the AND gate 6, the O
The R gate 7 and the serial interrupt signal output terminal 8 are interrupt signal output blocks 700 for the microprocessor.
Is formed.

The operation of the serial data receiving device configured as described above will be described with reference to the timing charts of the main parts shown in the configuration diagram of FIG. 1 and FIG.

First, FIG. 2A shows a clock signal waveform supplied to the serial clock terminal 1, and FIG. 2B shows a reset signal waveform supplied to the reset terminal 9. C, D, E, and F all show the output signal waveform of each bit of the shift register 100.
H shows an output signal waveform of each bit of the counter 200, FIG. 2I shows an output signal waveform of the D flip-flop 3, and FIG. 2J shows a serial data input terminal 12 3 shows the timing at which data supplied to the random access memory 300 is read.

In order to receive serial data by the device shown in FIG. 1, the state of the shift register 100 is set to [000
1] and the counter 200 and the D flip-flop 3 are reset. If a clock signal for reception is supplied to the serial clock terminal 1, the parallel output value of the shift register 100 is [1000], as shown in FIGS. 2C to 2F, each time its leading edge (leading edge) arrives. 〔01
00] ... [0000], and the output state of the counter 200 that counts the number of circulation of the output value also changes as shown in FIGS. 2G and 2H, and accordingly, from the serial data input terminal 12 The bit positions of the data written in the random access memory 300 are also switched. Thus, the timing signal generation circuit 500 is used to access the random access memory 3
When the timing signal supplied to 00 becomes active, the received data is written in the selected bit position. In this way, when the parallel output value of the shift register 100 becomes [0001] and the output of the first bit of the counter 200 becomes “0”, the level of the D terminal of the D flip-flop 3 shifts to “1”. As shown in FIG. 2I, the output level of the D flip-flop 3 shifts to "1" at the trailing edge (trailing edge) of the clock signal supplied to the serial clock terminal 1.

At this time, if the level applied to the interrupt prohibition terminal 11 is “0”, the level of the comparison enable terminal 401 shifts to “1”. In the digital comparator 400, the comparison data that has been supplied through the data bus 2 and the reception data stored in the random access memory 300 are compared with each other, and when both match, the output level of the digital comparator 400 is changed. The signal shifts to "1", the output level of the serial interrupt signal output terminal 8 also shifts to "1" as shown in FIG. 2K, and the interrupt request signal is sent to the microprocessor. As a result, since the microprocessor starts the interrupt processing routine, it is only necessary to read subsequent received data from the random access memory 300 via the data bus 2 by this interrupt processing routine. On the other hand, as a result of the comparison in the digital comparator 400, if they do not match, the output level of the serial interrupt signal output terminal 8 remains "0" and the interrupt request signal is not sent to the microprocessor.

In this way, in the serial data receiving apparatus shown in FIG. 1, the comparison data stored in advance in the digital comparator 400 can be freely set by the software installed in the microprocessor, and the received identification data And only when the comparison data matches
It is configured to capture subsequent information by interrupt processing. Therefore, the load on the software is considerably reduced. Further, a data buffer for storing the comparison data of the digital comparator 400 even when the unique data given to each processor as the identification data and the data common to the group given to the processor group including the processor exist. Prepare multiple pieces,
It is possible to deal flexibly by comparing the contents of each data buffer with the received data. Further, if the level of the comparison prohibition terminal 17 in FIG. 1 is set to "1", the output level of the serial interrupt signal output terminal 8 is set when the reception of one frame is completed regardless of the comparison result in the digital comparator 400. Shifts to “1”.

Note that FIG. 3 is a circuit connection diagram showing a specific configuration example of the random access memory 300, and a unit memory cell is composed of an inverter 301 and a three-state inverter 302. For example, the level (CK) of the serial data read clock input terminal 330 in FIG. 1 is “1”, and the level of the AND gate 303 to which the parallel output of the shift register 100 and the output signal of the counter 200 are supplied is also “1”. If so, the 3-state inverter 304 becomes active, and the data (SDA) at the serial data input terminal 12 is written in the memory cell via the SI terminal in FIG.

By the way, the timing signal generating circuit 500 of FIG. 1 is used to set the timing for reading the data from the serial data input terminal 12 into the random access memory 300, but its specific configuration is the essence of the present invention. Have no direct relation to each other, and therefore, only specific configuration examples and input / output signal timing charts are shown in FIGS. 4 and 5, respectively.

As is apparent from the above description, the serial data receiving apparatus of the present invention has memory means (random access) for parallel-converting the data string supplied to the serial data input terminal 12 and storing at least one frame. Memory 300),
Comparing means (digital comparator 400) for comparing the identification data stored in the memory means and indicating the destination of the data with the unique comparison data supplied via the data bus 2 for collating with the identification data; An interrupt signal output means for outputting the coincidence output of the identification data and the comparison data by the means as an interrupt request signal of the microprocessor, and fetching the subsequent information stored in the memory means by the interrupt processing routine of the microprocessor. Since the (interrupt signal output block 700) is provided, it is possible to realize a device that does not impose a burden on software and that allows easy setting and changing of comparison data, which is a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart of the main part of FIG. 1, and FIG. 3 is a circuit connection diagram showing a configuration example of a random access memory. 4, FIG. 4 is a circuit connection diagram showing a configuration example of the timing signal generating circuit, and FIG. 5 is a timing chart of the input / output signals of FIG. 2 ... Data bus, 12 ... Serial data input terminal, 30
0: Random access memory, 400: Digital comparator, 700: Interrupt signal output block.

Claims (2)

[Claims] 1. A memory means for parallel-converting a data string supplied to a serial data input terminal to store at least one frame, identification data stored in the memory means and indicating a destination of the data, and a data bus. Comparing means for comparing the identification data and the unique comparison data supplied for collation, and a coincidence output of the identification data and the comparison data by the comparing means is output as an interrupt request signal of the microprocessor, A serial data receiving device comprising interrupt signal output means for fetching subsequent information stored in the memory means by an interrupt processing routine of a processor. 2. A comparison inhibit terminal to which a disable signal for inhibiting comparison between the data of the first frame and the comparison data is supplied, an interrupt signal output terminal, and a memory means for storing the first frame of the first frame when the disable signal is supplied. 2. The serial data receiving apparatus according to claim 1, wherein the interrupt signal output means is constituted by a gate means that activates the interrupt signal output terminal when data storage is completed.