JPH0771257B2 - Vertical synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a countdown vertical synchronizing circuit used in a television receiver, and particularly, a reproduced image during special reproduction of a VTR (video tape recorder). The present invention relates to a vertical sync circuit that correctly takes the vertical sync.

(B) Conventional Technology There is a circuit as shown in FIG. 2 as a countdown vertical synchronizing circuit. In FIG. 2, the composite sync signal from the input terminal (1) is sync-separated by the sync separation circuit (2).
The horizontal sync signal separated in sync is a horizontal AFC circuit including a first phase comparator circuit (3), a VCO (voltage controlled oscillator circuit) (4), a frequency divider circuit (5) and a horizontal output circuit (6).
It is applied to (7) and the phase is compared with the flyback pulse from the horizontal output circuit (6) in the first phase comparison circuit (3). Then, the VCO (4) is controlled by the output according to the phase difference, and the oscillation output signal of the VCO (4) is synchronized with the horizontal synchronizing signal. Here, assuming that the oscillation frequency of the VCO (4) is, for example, 32f _H (where f _H is the horizontal synchronizing signal frequency), the frequency dividing circuit (5) performs 1/32 frequency division or 1/16 frequency division,
The signal of frequency f _H divided by 1/32 is applied to the horizontal output circuit (6), and the signal of frequency 2 f _H divided by 1/16 is the first D-
It is applied as a clock signal to the FF (8) and the vertical countdown circuit (9). The vertical countdown circuit (9) is constituted by a T-FF 10 stages connected in cascade, the frequency divider circuit (5) a signal of a frequency 2f _H from in the 10 stages of T-FF as a clock signal The first output signal φ ₁ is frequency-divided and outputs a frequency-divided output of each frequency division. The first output signal φ ₁ is the 8th vertical synchronization signal period after reset (H is one cycle of the horizontal synchronization signal, and 8H is The signal which becomes the “H” level at the timing when the 16 clock signals are counted) and the second output signal φ ₂ become the “H” level after the 224Hth period of the next vertical synchronizing signal period after being reset. Indicates a signal. In this state, when a normal vertical synchronizing signal from a broadcasting station of 262.5H is generated from the sync separation circuit (2), the vertical synchronizing signal is an AND gate (10) to which the second output signal φ ₂ is applied. ) To the first RS-FF (11) to set the first RS-FF (11). Then, the Q output becomes "H" level, and the D input of the first D-FF (8) becomes "H" level. 1st D-FF (8) C (clock)
Since the signal of the frequency 2f _H is applied to the terminal as the clock signal, its Q output becomes “H” level in response to the rising of the clock signal. The state is the third
Shown in the figure. FIG. 3 (a) shows the clock signal,
(B) shows the vertical synchronizing signal. If the rising edge of the vertical synchronizing signal is between the falling edges of the clock signal, 261.5H to 262H, as shown in FIG. 3B, the first D-FF (8) is output at the falling edge of 262H of the clock signal. Q output of becomes "H" level. Then, the vertical countdown circuit (9) and the first RS-FF (11) are reset, and the second RS-FF that operates as a vertical drive pulse generation circuit is also reset.
(12) is set, and its Q output becomes "H" level as shown in FIG. When the first RS-FF (11) is reset, its Q output becomes “L” level, and the first D-FF
The D input in (8) becomes "L" level. And the first D-
The Q output of FF (8) becomes "L" level in response to the fall of the 262.5H clock signal as shown in FIG. Therefore, the reset of the vertical countdown circuit (9) is released, and the counting operation is started again. Then, in response to the falling edge of the 8th H of the clock signal, the first output signal φ ₁ becomes the “H” level as shown in FIG. 3D and the second RS-FF (12) is reset, so that the second RS-FF is reset. 3rd for Q output of (12)
A vertical drive pulse as shown in FIG. 6 (e) is obtained, and the vertical output circuit (13) is driven.

Therefore, according to the circuit of FIG. 2, since the timing of the vertical synchronizing signal is synchronized with the clock signal corresponding to the horizontal synchronizing signal, it is possible to obtain the vertical drive pulse having a constant period and a constant width.

A vertical synchronizing circuit for synchronizing the incoming vertical synchronizing signal with a clock signal according to the horizontal synchronizing signal to obtain a vertical drive pulse as shown in FIG.
No. 172.

(C) Problems to be solved by the invention By the way, the vertical synchronizing signal in the video signal during the normal reproduction of the VTR has a cycle of 262.5H, which is the same as that from the broadcasting station. Therefore, the video signal can be correctly reproduced by the television receiver using the vertical synchronizing circuit shown in FIG. However, the vertical sync signal in the video signal during VTR special playback (while still or fast-forwarding) is called the pseudo-vertical sync signal, which is created and sent by the VTR itself, so its cycle is not always constant. Not exactly 262.5H in some cases. When such a pseudo vertical sync signal is applied to the vertical sync circuit of FIG. 2, the time interval between the vertical drive pulse and the luminance signal fluctuates according to the incoming pseudo vertical sync signal, and even fields and odd fields are detected. There is a problem in that the scanning lines are different and the reproduced screen looks like a double copy. This will be described with reference to the timing chart of FIG. Now, during special playback of VTR, its rise is 26 from the fall of clock signal 260.5H as shown in Fig. 4 (b).
Assuming that a pseudo vertical sync signal arrives during the fall of 1H, the Q output of 1D-FF (8) of FIG. 2 is generated according to the fall of the 261H clock signal of FIG. Is as shown in FIG. Then, the period of the vertical synchronizing signal (Fig. 4 (c)) next to the vertical synchronizing signal of Fig. 4 (b) is not constant, and there is a deviation of time A, from the fall of 261H to 261.5H.
Suppose it rises during the fall of. Then, the Q output of the first D-FF (8) becomes as shown in FIG. 4 (e) according to the signal of FIG. 4 (c), and the time B (clock signal There is a gap of (one cycle). The time B becomes larger than the time A. That is, 261H
Even if the rise of the pseudo vertical synchronizing signal is slightly deviated from the fall of the clock signal of the eye, a time lag of H / 2 occurs. When a vertical drive pulse is generated according to the signals shown in FIGS. 4 (d) and 4 (e), the above-mentioned reproduction screen will be duplicated.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and a sync separation circuit that separates a composite sync signal into a vertical sync signal and a horizontal sync signal in synchronization, and from the sync separation circuit Of a vertical non-standard discriminating circuit for discriminating whether or not the vertical synchronizing signal has a predetermined cycle, and an output control signal of the standard non-standard discriminating circuit. And a signal selecting circuit for selecting the vertical synchronizing signal or the output signal of the synchronizing circuit, and a vertical drive pulse is obtained according to the output signal of the signal selecting circuit.

(E) Operation According to the present invention, when the standard / non-standard discriminating circuit discriminates the standard, the vertical drive pulse is obtained according to the vertical synchronizing signal synchronized with the clock signal according to the horizontal synchronizing signal. Also, when it is judged as non-standard, the vertical drive pulse is obtained according to the vertical synchronizing signal, so even if a signal with a cycle shift occurs for every cycle, such as a pseudo vertical synchronizing signal from the VTR. The vertical drive pulse can be obtained with a minimum shift without expanding the shift.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. (14) is a vertical countdown circuit (14) to which a signal of frequency 2f _H from the frequency dividing circuit (5) is applied as a clock signal. 3) of 9)
The second phase in which the output signal φ ₃ is applied to the D input and the phase comparison between the Q output of the second D-FF (15) and the Q output of the first D-FF (8) is performed. A standard non-standard discrimination circuit composed of a comparison circuit (16), and (17) is a first AND gate to which the Q output of the first D-FF (8) and the output control signal of the standard non-standard discrimination circuit (14) are applied. (18), a second AND gate (19) to which the Q output of the first RS-FF (11) and the inverted signal of the output control signal are applied, and the first and second AND gates (18) and ( It is a signal selection circuit comprising an OR gate (20) to which the output signal of 19) is applied.

In FIG. 1, the same circuit elements as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

First, a description will be given of the normal reproduction of a VTR whose cycle is exactly 262.5H and the case where a vertical synchronizing signal is applied from a broadcasting station. As shown in Fig. 5 (b), the vertical synchronizing signal that rises between the falling of 261.5H and the falling of 262H of the clock signal (Fig. 5 (a)) is applied to the D input of the first D-FF (8). Then, the Q output is as shown in FIG. 5C and is applied to the standard / nonstandard discriminating circuit (14).

By the way, the second D-FF (15) and the second phase comparison circuit (16)
The standard non-standard discriminating circuit (14) includes a vertical synchronizing signal as a standard signal according to whether the rising edge of the vertical synchronizing signal is between the falling edge of 261.5H and the falling edge of 262H of the clock signal. Alternatively, the signal is discriminated as a non-standard signal, and the state of the signal selection circuit (17) is switched according to the discrimination result. The operation will be described. After the vertical countdown circuit (9) has been reset and the count has advanced to 261.5H, the third output signal φ ₃ is 261.5H as shown in FIG.
It becomes "H" level by eye, and the D input of the second D-FF (15) becomes "H" level. Then, in response to the fall of 262H of the clock signal applied to the C terminal of the second D-FF (15),
The Q output becomes "H" level as shown in FIG.
At the next 262.5H fall of the clock signal, since the vertical countdown circuit (9) has already been reset, the D input of the second D-FF (15) is already at "L" level. Therefore, the Q output is inverted to the “L” level, and the pulse shown in FIG. 5 (E) is applied to one input of the second phase comparison circuit (16). The other input of the second phase comparator circuit (16) is shown in FIG. 5 (c) of the first D-FF (8).
Since the Q output shown in is applied, the phases of both signals are compared. When the phases are the same as the signals shown in FIGS. 5 (c) and 5 (e), the second phase comparator circuit (16) generates a control signal of "H" value level indicating the standard state. , The first AND gate (18) is made conductive, and the second
Turn off the AND gate (19). Therefore, the signal (synchronized vertical synchronization signal) shown in FIG. 5C is set through the first AND gate (18) and the OR gate (20) to set the second RS-FF (12) which acts as a vertical drive pulse generation circuit. Applied to the input, its Q output rises as shown in FIG. Then, in response to the 8th falling edge of the clock signal, the first output signal φ ₁ becomes “H” level as shown in FIG.
Since the 2RS-FF (12) is reset, the vertical drive pulse as shown in FIG. 5 (f) is obtained at the Q output of the second RS-FF (12) to drive the vertical output circuit (13).

Next, a case where a pseudo vertical synchronizing signal generated during special reproduction of a VTR is applied to the circuit of FIG. 1 will be described. It is assumed that the period of the pseudo vertical synchronization signal is not constant, and the rising edge thereof is deviated by the front-back time A from the falling edge of the 261Hth clock signal, for example. Clock signal as shown in Fig. 6 (b) (Fig. 6 (a))
When a vertical synchronizing signal that rises from the fall of 260.5H to the fall of 261H is applied to the D input of the first D-FF (8), its Q output becomes as shown in Fig. 6 (d), It is applied to the standard / non-standard discrimination circuit (14) and to the reset terminal R of the vertical countdown circuit (9). When the vertical countdown circuit (9) is reset at the falling edge of the 261Hth clock signal, the 3rd output signal φ ₃ originally generated in response to the falling edge of the 261.5Hth clock signal cannot be generated and is at the “L” level. Keep Then, the D input of the second D-FF (15) becomes "L" level, and its Q output remains "L" level as shown in FIG. Therefore, in the second phase comparison circuit (16), the signal of FIG.
When the phase is compared with the signal of, the control signal of the "L" level indicating the non-standard state is generated at the output terminal thereof, and the first
The AND gate (18) is cut off and the second AND gate (19) is made conductive. In this state, Fig. 6 (b)
6 (c) whose period differs from that of the vertical synchronization signal of
Assuming that the vertical synchronization signal shown in FIG.
The signal of FIG. 6 (e) which is generated at the Q output of the first D-FF (8) in response to the vertical synchronizing signal of (1) cannot pass through the first AND gate (18), and the first RS-FF (11) ) Q output is the second
2nd R via AND gate (19) and OR gate (20)
Applied to the set input of S-FF (12). The first RS-FF
The rising edge of the Q output in (11) is equal to the rising edge of the vertical synchronizing signal in FIG. Therefore, the rising edge of the Q output of the second RS-FF (12) which functions as a vertical drive pulse generating circuit is also equal to the rising edge of the vertical synchronizing signal. Then, since the second RS-FF (12) is reset in response to the first output signal φ ₁ from the vertical countdown circuit (9), the vertical output circuit (13) has a vertical output signal as shown in FIG. A drive pulse can be obtained.

Now, FIG. 6 (g) shows a vertical drive pulse generated in response to the vertical synchronizing signal of FIG. 6 (b). When the signal of FIG. 6 (g) and the signal of FIG. 6 (h) are compared, the time difference is A, which is equal to the deviation A of the first cycle. That is, in the circuit of FIG. 1, when the incoming vertical synchronizing signal is determined to be a non-standard signal, the vertical drive pulse is obtained at the timing of the incoming vertical synchronizing signal.
It is possible to obtain the vertical drive pulse while maintaining the original deviation without increasing the deviation of the cycle between the incoming vertical synchronizing signals. Therefore, the adverse effect due to the deviation can be suppressed to a minimum and a vertical drive pulse having a stable cycle can be obtained.

(G) Effect of the Invention As described above, according to the present invention, when a pseudo vertical sync signal having a cycle other than 262.5H has arrived, such as during special reproduction of a VTR, it is determined as a non-standard state, and the pseudo vertical sync signal is generated. Since the vertical drive pulse is obtained according to the rising edge of the synchronizing signal, even if the period of the pseudo vertical synchronizing signal is not constant and there is a period shift for each signal, the shift is minimized without increasing the shift. The vertical drive pulse can be obtained with the deviation of. Therefore, the scanning lines of the even field and the odd field are the same, and the problem that the reproduced screen looks like a double copy is solved.

Further, according to the present invention, a vertical synchronizing signal from a broadcasting station or a VTR
When a vertical sync signal with a cycle of 262.5H, such as the vertical sync signal during normal playback, arrives, it is determined as the standard state, and the vertical sync signal is synchronized with the clock signal Since the drive pulse is obtained, the vertical drive pulse having a constant pulse width and cycle can be obtained, and stable vertical synchronization can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional vertical synchronizing circuit, FIGS. 3 (a) to (e) and FIGS. 4 (a) to (e). ) Is a timing chart for explaining the conventional vertical synchronizing circuit, and FIGS. 5 (a) to (g) and FIGS. 6 (a) to (h) are timing charts for providing the explanation of FIG. is there. (2) …… Synchronous separation circuit, (7) …… Horizontal AFC circuit,
(8) …… First D-FF, (14) …… Standard non-standard discrimination circuit,
(17) …… Signal switching circuit.

Claims (1)

[Claims] 1. A sync separation circuit for synchronizing and separating a composite sync signal into a vertical sync signal and a horizontal sync signal, a sync circuit for synchronizing a vertical sync signal from the sync separation circuit with the horizontal sync signal, and the horizontal sync signal. A vertical countdown circuit that divides a signal corresponding to the clock signal as a clock signal and is reset according to the output signal of the synchronizing circuit, a divided output signal of a vertical synchronizing signal period from the vertical countdown circuit, and an output of the synchronizing circuit. A standard non-standard discriminating circuit for discriminating whether or not the vertical synchronizing signal has a predetermined cycle by performing a phase comparison with a signal, and the vertical synchronizing signal or the synchronizing circuit according to an output control signal of the standard non-standard discriminating circuit. And a signal selecting circuit for selecting an output signal of the vertical selecting circuit, and a vertical driving pulse is obtained according to the output signal of the signal selecting circuit.