JPH0771258B2 - Vertical synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a countdown vertical synchronizing circuit used in a television receiver, and particularly, a reproduced image during special reproduction of a VTR (video tape recorder). The present invention relates to a vertical sync circuit that correctly takes the vertical sync.

(B) Conventional Technology There is a circuit as shown in FIG. 2 as a countdown vertical synchronizing circuit. In FIG. 2, the composite sync signal from the input terminal (1) is sync-separated by the sync separation circuit (2).
The horizontal sync signal separated in sync is a horizontal AFC circuit including a first phase comparator circuit (3), a VCO (voltage controlled oscillator circuit) (4), a frequency divider circuit (5) and a horizontal output circuit (6).
It is applied to (7) and the phase is compared with the flyback pulse from the horizontal output circuit (6) in the first phase comparison circuit (3). Then, the VCO (4) is controlled by the output according to the phase difference, and the oscillation output signal of the VCO (4) is synchronized with the horizontal synchronizing signal. Here, assuming that the oscillation frequency of the VCO (4) is, for example, 32f _H (where f _H is the horizontal synchronizing signal frequency), the frequency dividing circuit (5) performs 1/32 frequency division or 1/16 frequency division,
The signal of frequency f _H divided by 1/32 is applied to the horizontal output circuit (6), and the signal of frequency 2 f _H divided by 1/16 is the first D-
It is applied as a clock signal to the FF (8) and the vertical countdown circuit (9). The vertical countdown circuit (9) is T-FF and the decoder arrangement of 10 stages which are continuous connection, the 10-stage a signal of a frequency 2f _H from the frequency dividing circuit (5) as a clock signal T-FF The first output signal φ ₁ is divided in the following vertical synchronizing signal period after being reset.
At the 8Hth (H is one cycle of the horizontal synchronizing signal, 8H is the timing when 16 clock signals are counted), the signal which becomes the “H” level and the second output signal φ ₂ ) are reset. A signal which becomes the “H” level after the 224th H in the next vertical synchronizing signal period is shown. In this state, when a normal vertical synchronizing signal from a broadcasting station of 262.5H is generated from the sync separation circuit (2), the vertical synchronizing signal is an AND gate (10) to which the second output signal φ ₂ is applied. ) Via 1st RS-FF
It is applied to (11) and sets the first RS-FF (11). Then, the Q output becomes "H" level and the first D-FF
The D input in (8) becomes "H" level. 1st D-FF (8)
Since the signal of the frequency 2f _H is applied as a clock signal to the C (clock) terminal of, the Q output becomes "H" level in response to the fall of the clock signal.
This is shown in FIG. FIG. 3A shows the clock signal, and FIG. 3B shows the vertical synchronizing signal. If the rising edge of the vertical synchronizing signal is between the falling edges of the clock signal, 261.5H to 262H, as shown in FIG.
Q output of becomes "H" level. Then, the vertical countdown circuit (9) and the first RS-FF (11) are reset and at the same time, the first RS-FF (11) which operates as a vertical drive pulse generation circuit is reset.
2RS-FF (12) is set, and its Q output becomes "H" level as shown in FIG. When the first RS-FF (11) is reset, its Q output becomes “L” level,
The D input of the first D-FF (8) becomes "L" level. Then, the Q output of the first D-FF (8) is 26 as shown in FIG.
It goes to "L" level in response to the fall of the 2.5H clock signal. Therefore, the reset of the vertical countdown circuit (9) is released, and the counting operation is started again. Then, in response to the falling edge of the 8th H of the clock signal, the first output signal φ ₁
Becomes "H" level as shown in Fig. 3 (d), and the second RS-FF
Since (12) is reset, the vertical drive pulse as shown in FIG. 3 (e) is obtained at the Q output of the second RS-FF (12), and the vertical output circuit (13) is driven. By the way, the vertical synchronizing signal in the video signal during the normal reproduction of the VTR has a period of 262.5H, which is equal to that from the broadcasting station. Therefore, the video signal can be correctly reproduced by the television receiver using the vertical synchronizing circuit shown in FIG. However, the vertical sync signal in the video signal during VTR special playback (while still or fast-forwarding) is called the pseudo-vertical sync signal, which is created and sent by the VTR itself, so its cycle is not always constant. Not exactly 262.5H in some cases. A case where such a pseudo vertical synchronizing signal is applied to the vertical synchronizing circuit of FIG. 2 will be described with reference to FIGS.

Now, during the special reproduction of the VTR, if a pseudo vertical sync signal whose rising edge is between the falling edge of 261H and the falling edge of 261.5h of the clock signal as shown in FIG. The Q output of the first D-FF (8) becomes as shown in FIG. 3 (G) according to the fall of H. Then, the second RS-FF (12) is set according to the Q output, and the vertical drive pulse as shown in FIG.

Therefore, according to the circuit of FIG. 2, since the timing of the vertical synchronizing signal is synchronized with the clock signal corresponding to the horizontal synchronizing signal, it is possible to obtain the vertical drive pulse having a constant period and a constant width.

A vertical synchronizing circuit for synchronizing the incoming vertical synchronizing signal with a clock signal according to the horizontal synchronizing signal to obtain a vertical drive pulse as shown in FIG.
No. 172.

(C) Problems to be solved by the invention By the way, the rising edge of the vertical synchronizing signal during the special reproduction of the VTR is not always between the falling edge of 261H and the falling edge of 261.5H of the clock signal as shown in FIG. Do not repeat. For example, the first rising edge of the vertical sync signal is the clock signal 26
Even between the falling edge of 1H and the falling edge of 261.5H, the next rising edge of the vertical synchronizing signal is as shown in FIG. 3B, and this state may be repeated. In this case, Fig. 3 (b)
As can be seen from the comparison between the signal of FIG. 3 (f) and the signal of FIG. 3 (e) and the signal of FIG. 3 (h), the time difference A between the vertical synchronizing signals is When it is converted into a pulse, it becomes a time difference B and is enlarged. And time difference B
3 is applied to the deflection circuit in the subsequent stage, the time interval between the vertical period and the luminance signal period fluctuates in every vertical cycle, and even and odd fields There is a problem that the scanning lines are different and the reproduced screen looks like a double copy.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and a sync separation circuit for synchronously separating a composite sync signal into a vertical sync signal and a horizontal sync signal, and from the sync separation circuit A synchronizing circuit for synchronizing the vertical synchronizing signal with the horizontal synchronizing signal, and a vertical countdown circuit that divides a signal corresponding to the horizontal synchronizing signal as a clock signal and is reset according to an output signal of the synchronizing circuit, A phase comparison circuit for performing a phase comparison between the frequency division output signal of the vertical synchronization signal period from the vertical countdown circuit and the output signal of the synchronization circuit, and in response to the output signal of the phase comparison circuit being applied to a predetermined value or more. A standard non-standard discriminator composed of a discriminator that generates an output signal, and selects the vertical synchronizing signal or the output signal of the synchronizing circuit according to the output control signal of the standard non-standard discriminator. And a signal selection circuit for selecting.

(E) Operation According to the present invention, when the standard / non-standard discriminating circuit discriminates the standard, the vertical drive pulse is obtained according to the vertical synchronizing signal synchronized with the clock signal according to the horizontal synchronizing signal. Also, when it is judged as non-standard, the vertical drive pulse is obtained according to the vertical synchronizing signal, so even if a signal with a cycle shift occurs for every cycle, such as a pseudo vertical synchronizing signal from the VTR. The vertical drive pulse can be obtained with a minimum shift without expanding the shift.

Furthermore, according to the present invention, in the standard nonstandard discriminating circuit,
Since the output control signal is generated after detecting that the phase comparison result signal has exceeded the specified value, the vertical synchronization is stable even when the pseudo vertical synchronization signal with a special cycle arrives. Can be taken.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. (14) is a vertical countdown circuit (14) to which a signal of frequency 2f _H from the frequency dividing circuit (5) is applied as a clock signal. 3) of 9)
The second phase in which the output signal φ ₃ is applied to the D input and the phase comparison between the Q output of the second D-FF (15) and the Q output of the first D-FF (8) is performed. A standard non-standard discrimination circuit composed of a comparison circuit (16), and (17) is a first AND gate to which the Q output of the first D-FF (8) and the output control signal of the standard non-standard discrimination circuit (14) are applied. (18), a second AND gate (19) to which the Q output of the first RS-FF (11) and the inverted signal of the output control signal are applied, and the first and second AND gates (18) and ( It is a signal selection circuit comprising an agate (20) to which the output signal of 19) is applied.

In FIG. 1, the same circuit elements as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

First, a description will be given of the normal reproduction of a VTR whose cycle is exactly 262.5H and the case where a vertical synchronizing signal is applied from a broadcasting station. As shown in Fig. 5 (b), the vertical synchronizing signal that rises between the falling of 261.5H and the falling of 262H of the clock signal (Fig. 5 (a)) is applied to the D input of the first D-FF (8). Then, the Q output is as shown in FIG. 5C and is applied to the standard / nonstandard discriminating circuit (14).

By the way, the second D-FF (15) and the second phase comparison circuit (16)
The standard non-standard discriminating circuit (14) includes a vertical synchronizing signal as a standard signal according to whether the rising edge of the vertical synchronizing signal is between the falling edge of 261.5H and the falling edge of 262H of the clock signal. Alternatively, the signal is discriminated as a non-standard signal, and the state of the signal selection circuit (17) is switched according to the discrimination result. The operation will be described. After the vertical countdown circuit (9) has been reset and the count has advanced to 261.5H, the third output signal φ ₃ is 261.5H as shown in FIG.
It becomes "H" level by eye, and the D input of the second D-FF (15) becomes "H" level. Then, in response to the fall of 262H of the clock signal applied to the C terminal of the second D-FF (15),
The Q output becomes "H" level as shown in FIG.
At the next 262.5H fall of the clock signal, since the vertical countdown circuit (9) has already been reset, the D input of the second D-FF (15) is already at "L" level. Therefore, the Q output is inverted to the “L” level, and the pulse shown in FIG. 5 (E) is applied to one input of the second phase comparison circuit (16). The other input of the second phase comparator (16) is shown in FIG. 5 (c) of the first D-FF (11).
Since the Q output shown in is applied, the phases of both signals are compared. When the phases are the same as in the signals shown in FIGS. 5 (c) and 5 (e), the second phase comparison circuit (16) generates an "H" level control signal indicating the standard state, The first and gate (18) is made conductive and the second and gate (19) is made cut off. Therefore, the signal (synchronized vertical synchronization signal) shown in FIG. 5C is set through the first AND gate (18) and the OR gate (20) to set the second RS-FF (12) which acts as a vertical drive pulse generation circuit. Applied to the input, its Q output rises as shown in FIG. Then, in response to the 8th falling edge of the clock signal, the first output signal φ ₁ becomes “H” level as shown in FIG.
Since the 2RS-FF (12) is reset, a vertical drive pulse as shown in FIG. 5 (to) is obtained at the Q output of the second RS-FF (12) to drive the vertical output circuit (13).

Next, a case where a pseudo vertical synchronizing signal generated during special reproduction of a VTR is applied to the circuit of FIG. 1 will be described. It is assumed that the period of the pseudo vertical synchronizing signal is not constant, and the rising edge thereof is deviated by the front-back time A from the falling edge of the 261Hth clock signal, for example. Clock signal as shown in Fig. 6 (b) (Fig. 6 (a))
When a vertical synchronizing signal that rises from the fall of 260.5H to the fall of 261H is applied to the D input of the first D-FF (8), its Q output becomes as shown in Fig. 6 (d), It is applied to the standard / non-standard discrimination circuit (14) and to the reset terminal R of the vertical countdown circuit (9). When the vertical countdown circuit (9) is reset at the falling edge of the 261Hth clock signal, the 3rd output signal φ ₃ originally generated in response to the falling edge of the 261.5Hth clock signal cannot be generated and is at the “L” level. Keep Then, the D input of the second D-FF (15) becomes "L" level, and its Q output remains "L" level as shown in FIG. Therefore, in the second phase comparison circuit (16), the signal of FIG.
When the phase is compared with the signal of, the control signal of the "L" level indicating the non-standard state is generated at the output terminal thereof, and the first
The AND gate (18) is cut off and the second AND gate (19) is made conductive. In this state, Fig. 6 (b)
6 (c) whose period differs from that of the vertical synchronization signal of
Assuming that the vertical synchronization signal shown in FIG.
The signal of FIG. 6 (e) which is generated at the Q output of the first D-FF (8) in response to the vertical synchronizing signal of (1) cannot pass through the first AND gate (18), and the first RS-FF (11) ) Q output is the second
2nd R via AND gate (19) and OR gate (20)
Applied to the input to the set of S-FF (12). First RS-
The rising edge of the Q output of FF (11) is equal to the rising edge of the vertical synchronizing signal shown in FIG. Therefore, the rising edge of the Q output of the second RS-FF (12) which functions as a vertical drive pulse generating circuit is also equal to the rising edge of the vertical synchronizing signal. And
First output signal φ ₁ from the vertical countdown circuit (9)
In response to this, the second RS-FF (12) is reset, so that the vertical output pulse can be obtained from the vertical output circuit (13) as shown in FIG.

Now, FIG. 6 (g) shows a vertical drive pulse generated in response to the vertical synchronizing signal of FIG. 6 (b). When the signal of FIG. 6 (g) and the signal of FIG. 6 (h) are compared, the time difference is A, which is equal to the deviation A of the first cycle. That is, in the circuit of FIG. 1, when the incoming vertical synchronizing signal is determined to be a non-standard signal, the vertical drive pulse is obtained at the timing of the incoming vertical synchronizing signal.
It is possible to obtain the vertical drive pulse while maintaining the original deviation without increasing the deviation of the cycle between the incoming vertical synchronizing signals. Therefore, the adverse effect due to the deviation can be suppressed to a minimum and a vertical drive pulse having a stable cycle can be obtained.

Next, it is assumed that the period of the pseudo vertical synchronization signal is not constant and the rising edge of the pseudo vertical synchronizing signal deviates back and forth every cycle around the falling edge of the clock signal at 261.5H. Then, the first D-FF (8)
Signals (b) and (c) in FIG. 7 are alternately generated at the Q output of each of the cycles. On the other hand, the signal shown in FIG. 7D is generated at the Q output of the second D-FF (15). Therefore, the phases of the signals in FIGS. 7B and 7D are compared with those in FIGS. 7C and 7D every cycle. Then, the second
At the output terminal of the phase comparison circuit (16), control signals of "H" level and "L" level are generated every cycle. Therefore, the signal selection circuit (17) switches the signal to be taken in every cycle, and the vertical drive pulse whose phase is shifted by less than 2 clocks at the maximum at the output end of the second RS-FF (12) is taken every cycle. Will occur. Therefore, in the present invention, the control signal is generated after the output signal after the phase comparison is applied at a predetermined value or more. FIG. 4 is a circuit diagram showing an embodiment of the second phase comparator circuit (16) of FIG. 1, and (21) is the first D-FF.
A NAND gate to which the Q output of (8) and the clock signal from the frequency dividing circuit (5) are applied, and (22) is the Q output of the second D-FF (15) applied to the D input of the NAND gate (21). The output signal is applied to the clock input, and the third D-FF, (23), which operates as a phase comparison circuit, operates 8H of the next vertical synchronization signal cycle after the vertical countdown circuit (9) is reset.
Fourth output signal φ that goes to "H" level between the 16th and 16th eyes
₄ is applied to one input, and the Q output of the third D-FF (22) is applied to the other input, the third AND gate (24) has one input to which the fourth output signal φ ₄ is applied. Input to the first
4th AND gate to which output of 3D-FF (22) is applied,
(25) is a hexadecimal counter that counts the output signal of the third AND gate (23), (26) is an octal counter that counts the output signal of the fourth AND gate (24), and (27) is the The third RS-FF is set according to the output signal of the hexadecimal counter (25) and reset according to the output signal of the octal counter (26).

Next, the operation will be described. First D-FF as shown in Figure 7 (b)
When the Q output of (8) is input to one of the NAND gates (21), the output signal from the frequency dividing circuit (5) as shown in FIG. 7A is applied to the other input of the NAND gate (21). Therefore, the output signal of FIG. 7 (e) is generated at the output terminal. Here, an output signal as shown in FIG. 7D is generated at the Q output of the second D-FF (15) according to the second output signal φ ₃ . Therefore, the Q output of the 3D-FF (22) becomes "H" level and the output becomes "L" level in response to the fall of the signal of FIG. Then, the third AND gate (23) is turned on, and the fourth AND gate (24) is turned off, so that the fourth count from the vertical countdown circuit (9) is changed.
The output signal φ ₄ is applied to the hexadecimal counter (25) via the third AND gate (23).

At the next vertical cycle, the 1st D-FF as shown in Fig. 7 (c)
Since the Q output of (8) is applied to one input of the NAND gate (21), an output signal as shown in FIG. 7 (F) is generated at the output terminal of the NAND gate (21). At this time, 3D-
Since the D input of FF (22) is still at "L" level, when the signal of Fig. 7 (C) falls, the Q output of the 3D-FF (22) is output at "L" level. Is inverted to "H" level. Then, since the third AND gate (23) is turned off and the fourth AND gate (24) is turned on this time, the fourth output signal φ ₄ is transferred to the octal counter via the fourth AND gate (24). It is applied to (26). Then, this state continues for a while, and when the eight fourth output signals φ ₄ are applied to the octal counter (26), the output signal of the octal counter (26) becomes the “H” level and the hexadecimal counter (26). (25) and the third RS-FF (27) are reset. Then, the 3rd RS-FF
Since the Q output of (27) becomes "L" level, the signal selection circuit (17) selectively outputs the Q output of the first RS-FF (11) of FIG. Therefore, a vertical drive pulse having a rising edge equal to that of the vertical synchronizing signal can be obtained at the Q output of the second RS-FF (12) shown in FIG. Therefore, it is possible to accurately determine that the non-standard state is reached when the pseudo vertical synchronization signal having the special cycle as described above has arrived.

The hexadecimal counter (25) and the octal counter (26) reset the other counter when the output signal of one counter is generated. Therefore, once the discrimination is made, it is difficult to discriminate the opposite state, and erroneous discrimination is prevented.
Further, the count value of the counter does not necessarily have to be 16. The count value of the counter to which the output signal of the third AND gate (23) is applied may be larger than the count value of the counter to which the output signal of the fourth AND gate (24) is applied. Further, instead of the hexadecimal and octal counters (25) and (26), integrating circuits having different time constants may be used.

(G) Effect of the Invention As described above, according to the present invention, when a pseudo vertical sync signal having a cycle other than 262.5H has arrived, such as during special reproduction of a VTR, it is determined as a non-standard state, and the pseudo vertical sync signal is generated. Since the vertical drive pulse is obtained according to the rising edge of the synchronizing signal, even if the period of the pseudo vertical synchronizing signal is not constant and there is a period shift for each signal, the shift is minimized without increasing the shift. The vertical drive pulse can be obtained with the deviation of. Therefore, the scanning lines of the even field and the odd field are the same, and the problem that the reproduced screen looks like a double copy is solved. Further, according to the present invention, it is possible to reliably determine the case where the pseudo vertical synchronizing signal having a special cycle arrives as the non-standard state, so that a vertical drive pulse with a constant cycle and a constant pulse width is always generated. It is possible to obtain stable vertical synchronization.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional vertical synchronizing circuit, and FIGS. 3 (a) to 3 (h) are for explanation of FIG. FIG. 4 is a circuit diagram showing an embodiment of the standard / non-standard discrimination circuit of the present invention, FIGS. 5 (a) to 5 (g), and FIGS. 6 (a) to 6 (h).
7 (a) to 7 (f) are characteristic diagrams for explaining FIG. (2) …… Synchronous separation circuit, (8) …… First D-FF, (9)
...... Vertical countdown circuit, (14) …… Standard non-standard discrimination circuit, (17) …… Signal selection circuit, (22) …… 3D-F
F, (25) …… hexadecimal counter, (26) …… octal counter, (27) …… 3rd RS-FF.

Claims (1)

[Claims] 1. A sync separation circuit for synchronizing and separating a composite sync signal into a vertical sync signal and a horizontal sync signal, a sync circuit for synchronizing a vertical sync signal from the sync separation circuit with the horizontal sync signal, and the horizontal sync signal. A vertical countdown circuit that divides a signal corresponding to the clock signal as a clock signal and is reset according to the output signal of the synchronizing circuit, a divided output signal of a vertical synchronizing signal period from the vertical countdown circuit, and an output of the synchronizing circuit. A standard non-standard discriminator circuit comprising a phase comparator circuit for performing phase comparison with a signal and a counter for counting output signals of the phase comparator circuit and generating an output when the count value reaches a predetermined value; And a signal selection circuit for selecting the vertical synchronization signal or the output signal of the synchronization circuit according to an output control signal, according to the output signal of the signal selection circuit. Vertical synchronizing circuit, characterized in that to obtain the direct drive pulses.