JPH0773274B2 - Address determination circuit for transmission device terminal - Google Patents

Description

TECHNICAL FIELD The present invention relates to an address determination circuit in a transmission system in which a plurality of stations are connected to a transmission line.

[Conventional technology]

There is a data transmission system between a plurality of terminals in a premises or between terminals across a plurality of premises. For example, LAN
(Local Area Network) is one of them. For example, there is a "data communication handbook" (edited by The Electronic Society of Japan, issued October 30, 1984, page 121).

An example of the transmission system is shown in FIG. FIG. 3 has three loop-shaped transmission lines 50, 51, 52, and a computer 50A and terminals 50B, 50C are connected to the loop-shaped transmission line 50. The computer 50A may also be considered a terminal in a broad sense. Terminals 51A and 51B were connected to the loop-shaped transmission line 51, and were connected to other loop-shaped transmission lines via the terminal 50C. Terminals 52A, 52B,
52C is connected and the loop-shaped transmission line 50 is connected via the terminal 50B.

The loop transmission lines 50, 51, 52 are called rings.

Data transmission of this transmission system is performed in frame units, and the data format of one frame is shown in FIG. A delimiter DEL that plays the role of a synchronization code is placed at the beginning and the end of one frame, and then a destination address part DA, a source address part SA, transmission information I, and a check code FCS are provided.

In this frame structure, the address parts DA and SA are each composed of several bytes. The reason we need these few bytes is
This is because each ring has an address, each station (terminal) address is required in the ring, the ring is designated by the group, and the station is designated by the group.

FIG. 5 shows a specific detailed configuration of the destination address part DA.
DA consists of:

Station type address IGA that specifies whether the transmission frame is addressed to a single station or all stations (or addressed to a single station or a group specification that specifies multiple stations).

Ring number address LA that specifies the ring to which the other station belongs.

 Station address STA of the sending station.

Further, as shown in FIG. 6, LA designates a single ring or all rings, and STA designates individual, group or all stations.

As described above, since there are various kinds of addresses, how to efficiently determine the address is a problem at each terminal station.

A conventional address determination procedure will be described with reference to FIG. In order to determine whether or not the destination address DA is addressed to the own station, the DA itself is further decomposed into DA1, DA2, ..., DAn.
This division is performed, for example, with 1 byte which is a basic unit amount for address display. Each 1 byte indicates a ring, a station, etc., and also indicates whether the group or individual.

On the other hand, each terminal has a reference address MA for address comparison. The reference address MA indicates a self address of the terminal and the like, and is a value unique to the terminal. Also for this MA, DA1, MA2,…, MAn
And split.

Between this divided DA1 to DAn and MA1 to MAn, DA1 and MA1 →
Address comparison is performed sequentially as DA2 and MA2 →. The comparison by this division is characterized in that the comparison procedure becomes long, and for each divided subdivision address DAi and MAi, the content of the comparison process is not single but different if i is different.

FIG. 8 shows a series of processes for such address determination. IGA1
The address composed of 7 bits, LA 7 bits, and STA 16 bits is divided into 1 byte (8 bits), and determination is performed 3 times for each division unit. In the figure, three determination processes are shown. The view of this figure means that one DA is divided into three, and different division determination processing is performed for each division unit (DA1, DA2, DA3: MA1, MA2, MA3). Judgment process 1
In (address comparison of DA1 and MA1), it is determined whether individual or group, whether it is the own ring, whether all 1 (all1) or all 0 (all0). Process 2 (DA
2) and MA2 address comparison), whether or not it is addressed to the own ring, all1 whether it is all0, processing 3 (DA3 and MA3 address comparison)
Then, processing for whether or not it is addressed to its own station and whether it is addressed to its own station is performed.

All in ring number address LA processing
1, all 0 indicates all rings, and in all other cases, the ring has an address matching the LA value. When the address is divided into units of, for example, 1 byte (8 bits) and the addresses are compared every 8 bits, the first 1 bit indicates the IGA and the next 7 bits indicate the ring address.
When the 7 bits are all 1's or all 0's, all rings are addressed. For example, "0001010" is addressed to the ring designated by the address. Station address ST
The same applies to the case of A. When all 1 (or all 0) is set, all stations are addressed, and in other cases, the station is addressed to the address designated by the value of STA.

That is, in the judgment processing 1, whether the received frame is addressed individually or to the group, if it is addressed individually, whether it matches the address of the receiving station itself, or whether it is a broadcast frame, and if it is addressed to the group, , It is necessary to judge whether or not it matches with the group address to which the receiving station belongs, but in the judgment processing 2-3, based on the result of the judgment processing 1, if it is an individual address, the address of the receiving station itself It is sufficient to compare and check whether the frame is a broadcast frame or not, and if it is a group, determine whether it is a group to which the receiving station belongs. Become. FIG. 9 shows the time required for the determination process.
The period between T _{0 and} T ₁ is the time required for frame transmission for each unit amount described above. That is, the receiving station of the frame results in the data of the unit quantity for each at an interval of T ₀ T ₁ comes entering a port, it is necessary to terminate the determination process in the T ₀ T ₁ of time, the determination process 1 Similarly, if the amount of processing per unit amount increases, it may not be possible to make a judgment within the time T ₀ T ₁ and the time frame may be exceeded (T ₀ T ₂ ). Therefore, when configuring the address determination circuit, it is necessary to buffer and reduce the difference in determination time depending on the amount of determination as described above.

As a conventional method 1, there is a method of providing a storage circuit capable of storing all the destination addresses of the received frame for each unit quantity as shown in FIG. With this method, the entire destination address can be held until the next frame is received, so the difference in the determination time due to the amount of determination can be buffered, but the drawback is that the circuit amount increases as the total amount of destination addresses DA increases. is there.

Further, as the conventional method 2, there is a method of successively storing the destination address of the received frame in one storage circuit for each unit amount as shown in FIG. With this method, the address judgment circuit can be made smaller, but since the judgment process must be performed within a fixed time, as described above, if the processing amount per unit amount increases, the destination address is held per unit amount. There is a drawback that it cannot be judged in time.

[Object of the Invention]

An object of the present invention is to compare the destination address of the frame with the address of the own station at the station that has received the transmission frame as described above, and when determining whether the frame is addressed to the own station,
An object of the present invention is to provide an address determination circuit which is small and can be processed at high speed regardless of the amount of determination.

[Outline of Invention]

The present invention provides a plurality of circuits that store a destination address of a received frame for each unit amount when a station that receives the frame determines whether the frame is addressed to itself.
By sequentially storing the data, the retention time of the data for each storage circuit is extended, and the determination time different for each unit amount is buffered. In addition, the number of memory circuits can be minimized to reduce the size of the circuits.

Example of Invention

FIG. 1 shows an embodiment of the station receiver of the present invention. This station receiver is provided individually for each station. The station receiver comprises a serial / parallel conversion circuit 11, a shift register 3, and an address conversion circuit 14.

The address conversion circuit 14 includes a conversion detection circuit 15, a selection circuit 16, an inverter 17B, AND gates 17A and 17C, and flag registers 22 and 2.
3, Comprising storage circuits 18 and 19, comparison circuit 20, and receiving station address setter (register) 21.

The station receiving the frame performs serial-parallel conversion for converting the frame of the transmission line, which is the serial data 10, into parallel data for each unit amount. The data converted into the parallel data 12 by the serial-parallel conversion circuit 11 is sequentially transferred to the shift register 3 and the reception buffer.Whether the data is transferred to the reception buffer, that is, whether the reception frame is addressed to itself. It is the address determination circuit 14 that outputs the transfer permission signal 23 to the reception buffer. Of the data converted into the parallel data 12, the destination address DA is transferred to the address determination circuit 14 as well as the transfer to the shift register 3. The destination address DA14 transferred to the address determination circuit 14 is sequentially and alternately stored in the storage circuits 18 and 19 for each unit amount converted by the serial-parallel conversion circuit 11. The storage circuit to be stored is selected by the selection circuit 16 that generates and outputs the storage circuit selection signal 17. That is, by changing the logical value of the memory circuit selection signal 17 output from the selection circuit 16 to 1 or 0, the destination address per unit quantity transferred to the address determination circuit 14 as parallel data 12 from the serial-parallel conversion circuit 11
The DA 14 is distributed to the memory circuit 18 or the memory circuit 19. The logical value of the memory circuit selection signal 17 is changed by the memory circuit.
Selection circuit control signal 29 output from the comparison circuit 20 that compares the destination address DA for each unit amount stored in 18 or 19 with the receiving station address 21 that stores the address of the receiving station itself
Is. For example, if the storage circuit 18 is selected when the storage circuit selection signal 17 has a logical value of 1 and the storage circuit 19 is selected when the storage circuit selection signal 17 has a logical value of 0, the storage circuit selection signal 17 is divided into unit capacitors when the storage circuit selection signal 17 has a logical value of 1. The destination address DA14 is stored in the memory circuit 18, and at the same time, the flag register 22 indicating that the data is stored in the memory circuit 18 is set, and the flag set signal 24 indicating the set of the flag register 22 is output to the comparison circuit 20. . Comparing circuit 20 which detects the set of flag register 22
The selection circuit control signal 29 instructs the selection circuit 16 to change the logical value of the storage circuit selection signal 17 from 1 to 0. Moreover, the flag 22 is set by using the flag clear signal 30.
Is cleared, the data stored in the memory circuit 18 is read, and the data at the receiving station address 21 is compared. By changing the logical value of the memory circuit selection signal 17 from 1 to 0 as described above, the next destination address DA divided as described above is generated.
Are stored in the memory circuit 19. In this way, the destination address DA is alternately stored in the two storage circuits for each unit amount and compared with the own station address. As a result of the comparison, if the received frame is addressed to the own station, the comparison circuit 20 outputs the transfer permission signal 23 to the reception buffer. Here, the shift register 3 is installed because it determines whether or not the received frame is addressed to the own station and outputs the transfer permission signal 23 to the reception buffer, and it saves only the frame addressed to the own station. This is to transfer to the reception buffer.

Two advantages are created by configuring the address determination circuit as described above. The first advantage is that the data retention time of each memory circuit can be doubled by installing two memory circuits, so that the difference in determination time due to the amount of processing per unit amount of destination address is buffered, And the judgment can be slow,
The second advantage is the miniaturization of the circuit by minimizing the storage circuit of the data per unit amount of the destination address.

First, the buffering of the difference in determination time, which is the first advantage, will be described. The destination address DA is, as shown in FIG. 5, an address IGA indicating individual / group, a ring address LA, and a station address ST indicating the station number to receive the frame.
As shown in FIG. 6, the station address STA is composed of A, and includes information such as an address addressed to an individual station, a broadcast address or a group address. The ring address LA contains the identification of a single ring or all rings. Also, when performing address determination, as shown in FIG.
Address MA of the receiving station itself divided into DA1, DA2, ... DAn
However, the processing amount per divided unit amount differs depending on the information contained in the unit amount.

That is, the above-mentioned DA1 includes an I / G indicating whether it is addressed individually or a group, and a ring number indicating which ring the received frame is addressed to. Therefore, when the address of DA1 is determined, it is first determined whether the received frame is addressed individually or to a group as shown in the determination processing 1 in FIG. 8, and then the ring number is determined. If it is recognized that the frame is addressed to the individual, then the individual ring number is judged to determine whether it is addressed to the ring to which the frame receiving station belongs. After performing the individual ring number determination, whether the received frame is addressed to all rings regardless of whether the ring number included in DA1 matches or does not match the ring number to which the receiving station belongs (all1 or
It is determined whether it is a broadcast frame or not). For example, when it is determined in the individual ring number determination that the frame is addressed to the ring to which the receiving station belongs, it is necessary to recognize whether or not the frame is addressed to all the rings. Even if it is determined by the individual ring number determination that the receiving station is not addressed to the ring to which the receiving station belongs, the frame must be received when the addresses are addressed to all the rings. Since the determination of such a DA1 there are a wide determination conditions, the determination time increases, the transmission time of a frame for each quantity determination unit, i.e. the determination process can be no longer between T ₀ through T ₁ in FIG. 9 T ₂ The phenomenon that it extends to occurs. On the other hand, in the determination of DA2, since it has already been determined whether the frame already received by DA1 is addressed to the individual ring or the group, as shown in the determination processing 2 in FIG. Since it is only necessary to check whether or not the judgment is made, the judgment processing can be performed between T _{0 and} T ₁ like the judgment processing 2 in FIG. As described later, the determination amount gradually decreases as shown in the determination process 3 in FIG. 8, and the determination time is the transmission time per unit of frame, that is, T _0.
It will settle between ~ T ₁ .

Here, as shown in FIG. 1, if two storage circuits per unit quantity of the destination address are installed and data is stored alternately, the data holding time per storage circuit is as shown in FIG. It is twice as large as that of one memory circuit. Therefore, since the determination process is also performed in the double time frame, it is possible to sufficiently deal with the determination exceeding the processing time frame per unit amount like the determination process 1 in FIG. Where T _{0 to} T ₁ , T _{1 to} T ₂ , T _{2 to} T ₃ , T _{3 to} T ₄ ,
... is the time when data for each unit amount comes in.

The second advantage will be described in comparison with FIGS. 10 and 11. As described above, in order to buffer the difference in the determination time due to the processing amount per destination address unit amount, it is conceivable to provide a memory circuit capable of storing all destination addresses as shown in FIG. This method is disadvantageous in miniaturizing the circuit because the amount of the circuit increases as the capacity of the destination address increases. On the other hand, if two memory circuits are installed as shown in Fig. 1 and stored alternately, the difference in judgment time is buffered as described above, and it is about 50% smaller than the destination address full storage method. Can be converted.

As a modification of the present invention, there is a method of determining the destination address DA and the receiving station address MA of the received data by software.

〔The invention's effect〕

According to the present invention, when receiving a frame on a transmission line and making a comparison judgment of the destination address of the frame and the address of the receiving station itself, there is an effect that the difference in processing time per judgment unit amount can be buffered.

Further, according to the present invention, the address judgment circuit is reduced to about half
There is an effect that can be miniaturized.

[Brief description of drawings]

FIG. 1 is an embodiment diagram of the present invention, FIG. 2 is an operation explanatory diagram thereof,
FIG. 3 is an example of an object of the present invention, FIGS. 4, 5, and 6 are data format diagrams, FIG. 7 is an example of determination processing, and FIG. 8 is a diagram showing a procedure of determination processing. FIG. 9 is a diagram showing the relationship between the determination process and time, and FIGS. 10 and 11 are conventional examples. 50,51,52 …… Loop transmission line, 50A, 50B, 50C, 51A, 51B, 52
A, 52B, 52C ... Terminal, 14 ... Address judgment circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shunji Inada 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-59-105738 (JP, A) JP-A-57 -201934 (JP, A)

Claims (1)

[Claims] 1. An address judgment circuit, wherein each terminal judges a destination address of a received frame in data transmission between terminals of a transmission device of a network configured by connecting a plurality of ring-shaped transmission lines, the received frame Is configured by adding transmission information to a destination address having at least a ring address and a terminal address, and the destination address specifies its own station by dividing the destination address into a plurality of addresses and sequentially performing address comparison for each divided portion. In the address determination circuit of the transmission device terminal that determines whether or not there is a serial-parallel conversion unit that converts a received frame into parallel data for each division unit amount, two storage units, and a received frame that is converted into parallel data. Correspondence between the means for storing the destination address alternately in each of the divided unit amounts in the two storage means and the content of each storage means Comparison determination means for sequentially comparing the received station division address with each other, delay means for outputting the reception frame converted into the parallel data with a time delay, and the comparison determination means for all destination addresses of one reception frame. An address determination circuit of a transmission device terminal, comprising: a reception buffer that takes in a reception frame output from the delay means only when it is determined that it is addressed to its own station.