JPH077338B2 - Parallel processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an instruction processing mechanism of a microprocessor.

2. Description of the Related Art In recent years, software programming type microprocessors have been widely used in all fields, and as a configuration thereof, a program storage means for storing a program including a group of instructions to be sequentially executed and a plurality of addresses are provided. Data input / output means whose address is specified by an instruction stored in the program storage means, arithmetic means for executing data arithmetic based on the instruction transmitted from the program storage means, and the data input / output means (data A memory or an input / output port corresponds thereto) and a data bus for coupling between the arithmetic means are provided. A typical structure thereof is shown in Japanese Patent Publication No. 58-33584.

Such a software programming type microprocessor can be used for all purposes, but on the other hand
In order to use it as a controller for some devices that require high-speed processing, there is a problem in that it lacks real-time processing capability as compared with a dedicated controller configured with a wired logic. A pipeline processing method is adopted to increase the processing capability of the microprocessor, or a microprocessor having a multi-processing configuration as shown in U.S. Pat.No. 3,980,992 and Japanese Patent Application Publication No. 62-69351 is proposed. Came.

However, although the pipeline processing method pre-reads an instruction in advance to improve the execution efficiency of the instruction, if a conditional branch instruction or the like is included, the exception processing is performed. There are inconveniences such as complication and inability to obtain the look-ahead effect. Also, in a microprocessor with a multi-processing configuration, a plurality of processing loops are executed in a time-sharing manner in order to share resources such as an ALU (arithmetic-logical operation unit) and a data bus, but real-time processing is improved. There was a problem that the processing efficiency was not improved.

In view of the above problems, the present invention aims to improve the processing efficiency of a microprocessor having a multi-processing configuration, more than ever before.

Means for Solving the Problems In order to solve the above-mentioned problems, the parallel processor of the present invention causes the second instruction selecting unit to select the instruction subsequent to the instruction selecting by the first instruction selecting unit,
A context controller that alternately allocates the execution cycles of the instructions selected by these instruction selecting means, and an instruction selected by one instruction selecting means is a branch instruction with an operand having address information next to the instruction code. An instruction discriminator for discriminating whether or not there is a branch instruction detection signal from the instruction discriminator, and the address information of the branch instruction is transmitted to the instruction selection means by the next execution cycle by the instruction selection means. An instruction fetch controller is provided for executing an instruction from the branch destination address.

In the present invention, with the above-mentioned configuration, if the instruction fetched from the second instruction selecting means is accompanied by the branch address,
During execution of the instruction fetched from the first instruction selecting means,
That is, the processing efficiency of the microprocessor is substantially improved by updating the address of the second instruction selecting means by the time the execution of the instruction fetched from the second instruction selecting means is started.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a parallel processor according to an embodiment of the present invention, in which a first programmable counter (PC1) 2 from an instruction ROM 1 in which a program including an instruction group to be sequentially executed is stored. Alternatively, the instruction selected by the second programmable counter (PC2) 3 is sent to the instruction queue 4 for holding and prefetching the instruction. In the instruction queue 4, the instruction once held is sent to the instruction decoder 5, and the address index portion thereof is sent to the address bus 6, the first programmable counter 2 and the second programmable counter 3. The control signal group generated by the instruction decoder 5 is supplied to each block forming the microprocessor via the control bus 7. Further, a plurality of timing signals for processing of the microprocessor are generated in the timing generator (TG) 8, and these timing signals are supplied to each block via the control bus 7. The address bus 6, the first address register (ADR1) 9, the second address register (ADR1) 10, and the data bus 11 are connected to each other so as to exchange address data. The first address register 9 and the second address register 10 hold addresses of a RAM (including a stack area) 12 and a general-purpose parallel input / output port (PIO) 13.
The three groups of input / output lines of the general-purpose parallel input / output port 13 are
They are connected to the input / output terminal groups of the A, B, and C groups, which are composed of terminals A0 to A15, terminals B0 to B15, and terminals C0 to C15, respectively. Further, the input part of the ALU 16 is connected to the data bus 11 via a first register (AX) 14 and a second register (AY) 15, and the output of the ALU is an accumulator unit (ACC) (also a flag group). Included.) Supplied to 17. The accumulator unit 17 and the data bus 11
Between the two are also connected by a bidirectional bus.

On the other hand, the timing signal from the timing generator 8 is also supplied to the context controller 18, and the output signal of the context controller 18 is supplied to the accumulator unit 17 and the instruction fetch controller 20 as an instruction execution cycle identification signal for address setting. It is supplied to the second address register 10 as an operation enable signal, and an inverted signal via the inverter 19 is supplied to the first address register 9. A count clock signal and a preset signal are supplied from the instruction fetch controller 20 to the first programmable counter 2 and the second programmable counter 3, respectively. The command from the command ROM 1 is also supplied to the command discriminator 21, and the command fetch controller 20 is supplied with a count update command signal from the command discriminator 21 and a preset command signal from the command decoder 5. The contents of the zero flag and carry flag are supplied from the accumulator unit 17, respectively. Further, the instruction queue 4 includes a first buffer 4A and a second buffer 4A.
4B, a third buffer 4C, a fourth buffer 4D, the first buffer 4A and the second buffer 4B form a FIFO (first in first out) type stack, and by the first programmable counter 2 The first byte of the fetched instruction and the second programmable counter 3
The first byte of the instruction fetched by is stored alternately one after another.

It is assumed that the data output section of each block has a 3-state configuration and is held in a high impedance state during a period in which data output is not required. Further, each block is supplied with necessary timing signals and control signals via the control bus 7.

Regarding the parallel processor configured as above,
The operation will be described with reference to the configuration diagram shown in FIG. 1 and the timing chart of the main part shown in FIG. 2A shows an external clock signal waveform supplied to the CLK terminal of FIG. 1,
2B is an instruction decoding period by the instruction decoder 5, FIG.
Ca is the timing when the instruction fetch controller 20 presets the first programmable counter 2, FIG. 2Cb is the timing when the instruction fetch controller 20 presets the second programmable counter 3, and FIG. 2D is the instruction
The operation period of the first programmable counter 2 with respect to the ROM1, FIG. 2E is the precharge period of the decoder section of the instruction ROM1, and FIG. 2F is the transfer timing of the instruction code from the instruction ROM1 to the second buffer 4B of the instruction queue 4. 2G shows the timing of increment of the first programmable counter 2 or the second programmable counter 3 when reading a 2-byte instruction, and FIG. 2H shows the instruction operand from the instruction ROM 1 to the fourth buffer 4D of the instruction queue 4. 2 is the transfer timing of the instruction code from the second buffer 4B to the first buffer 4A of the instruction queue 4, and FIG. 2J is the transfer timing of the fourth buffer 4D to the third buffer 4C of the instruction queue 4. The transfer timing of the instruction operand, FIG. 2K is from the third buffer 4C of the instruction queue 4 to the first programmable counter 2 and the second programmable counter 2. Change in the preset data supplied to grammar table counter 3, FIG. 2 L is an illustration of each execution cycle identification signal outputted from the context controller 18.

Now, in the parallel processor of FIG.
The instruction fetched from is temporarily held in the instruction queue 4, and then the instruction decoder 5 interprets the processing contents and executes the instruction.

Here, the section a in FIG. 2 is allocated to the execution section of the instruction fetched by the first programmable counter 2, and the section b is allocated to the execution section of the instruction fetched by the second programmable counter 3. In addition,
The accumulator unit 17 is separately provided with an accumulator and a flag group used in the section a and an accumulator and a flag group used in the section b, and their selection is based on the execution cycle identification signal supplied from the context controller 18. The context controller 18 also switches between the first address register 9 and the second address register 10.

In order to start the execution of the conditional branch instruction at time t0 and execute the instruction at the branch destination from time t2, the instruction decoding, the determination of the branch condition, the first branch destination address Preset, command to programmable counter 2
The transfer of the instruction code from the ROM 1 to the second buffer 4B of the instruction queue 4 and the transfer of the instruction code from the second buffer 4B to the first buffer 4A may be completed. The parallel processor of FIG. 1 decodes the instruction at the timing of FIG. 2B, and if it is a conditional branch instruction, the instruction decoder 5 sends a preset instruction signal to the instruction fetch controller 20. Instruction fetch controller 20
If the branch condition is satisfied by determining the contents of the zero flag and the carry flag supplied from the accumulator unit 17, the third buffer 4C of the instruction queue 4 supplies the first programmable counter 2 at the timing of Ca in FIG. The first programmable counter 2 based on the address information (branch destination absolute address or relative address information, which is supplied at the timing of FIG. 2K).
Preset. Further, at the timing of FIG. 2D, the counter that supplies the count value to the decoder section of the instruction ROM 1 is switched to the first programmable counter 2, and based on the new preset value, it is shown by the solid line in FIG. 2E. At the timing, the decoder section of the instruction ROM1 is precharged (set up). When the precharge is completed, the first byte of the instruction code is fetched from the instruction ROM 1 at the timing of FIG. 2F, stored in the second buffer 4B of the instruction queue 4, and supplied to the instruction discriminator 21. The instruction discriminator 21 discriminates the supplied instruction code, and if it is a branch instruction and is an instruction accompanied by an operand having address information, the instruction discriminator 21 uses the instruction fetch controller as a branch instruction detection signal. A count update command is sent to 20 and, as a result, FIG.
At this timing, the instruction fetch controller 20 increments the first programmable counter 2 or the second programmable counter 3 and the second precharge of the decoder section of the instruction ROM 1 is performed at the timing indicated by the alternate long and short dash line in FIG. 2E. . When the second precharge is completed, at the timing of FIG.
The second byte of the instruction code is extracted from and stored in the fourth buffer 4D of the instruction queue 4. The instruction code of the second byte stored in the fourth buffer 4D is transferred to the third buffer 4C of the instruction queue 4 at the timing of FIG. 2J, and immediately after that, as shown in FIG. 2K, New preset data is supplied to the programmable counter 1 of 1. On the other hand, the instruction code stored in the second buffer 4B of the instruction queue 4 is
It is transferred to the first buffer 4A and prepared for instruction decoding from the subsequent time t2.

Therefore, the instruction at the branch destination can be executed from time t2. That is, in the parallel processor shown in FIG. 1, between the a section which is the execution section of the instruction fetched by the first programmable counter 2 and the a section,
By utilizing the existence of the b section which is the execution section of the instruction fetched by the second programmable counter 3, for the a section, the instruction at the branch destination is completed by the end of the b section which is the back cycle of the instruction execution. You have completed the necessary preparations to do.

Although the conditional branch instruction has been described in the above description,
In the case of an unconditional branch instruction, only the condition determination is not necessary, and the branch address can be fixed in the back cycle of the instruction execution in the same manner, and the same applies to the subroutine call instruction.

In this way, in the parallel processor shown in FIG. 1, the instruction fetched from the first programmable counter 2 or the second programmable counter 3 is a so-called 2-cycle instruction, which is accompanied by a preset operation of the programmable counter. Even with an instruction, the preparation for executing the instruction at the branch destination can be completed by the start of the next execution cycle of each section, and the processing efficiency of the microprocessor can be substantially improved.

By the way, in the embodiment shown in FIG. 1, the first and second
Although the parallel processing processor having the double processing mechanism having the programmable counter has been described, it goes without saying that the present invention can be similarly applied to the parallel processing processor having the multiple processing mechanism.

FIG. 3 shows another embodiment of the present invention. In this example, the present invention is applied to a parallel processor having a triple processing mechanism. In the apparatus of FIG. 3, the context controller 18 is connected to the accumulator unit 17, the first address register 9, the second address register 10, the third address register 22, and the instruction fetch controller 20 in FIG. Three types of identification signals such as Lb and Lc are transmitted. Based on these identification signals, the instruction fetch controller 20 supplies the count clock signal and the preset signal to the first programmable counter 2, the second programmable counter 3, and the third programmable counter 23 at necessary timings. Note that FIG. 4 is a timing chain of the main part of the microprocessor shown in FIG. 3, which is compared with FIG.

As can be seen from FIG. 4, in the parallel processor shown in FIG. 3, when the execution of the conditional branch instruction is started at the time t0 when the a section starts, the branch is started from the time t3 when the next a section is started. The above instruction can be executed, and the processing efficiency of the microprocessor can be improved similarly to the parallel processor shown in FIG.

As is apparent from the above description, the parallel processor of the present invention includes a program storage unit (instruction ROM 1) for storing a program including a group of instructions to be sequentially executed, and a specific storage unit stored in the program storage unit. At least first and second instruction selecting means (first programmable counter 2 and second programmable counter) for designating an address to the program storing means for selecting the instruction and selecting the instruction stored at the address. 3), an arithmetic means (ALU16) for executing arithmetic operation of data based on the instruction sent from the program storing means, a timing generator 8 for generating an instruction execution cycle, and an instruction by the first instruction selecting means. Selection of the instructions by the second instruction selecting means, and the selection of these instructions is performed. The context controller 18 for alternately allocating the execution cycles of the instructions selected by the means, and whether the instruction selected by one of the instruction selecting means is a branch instruction with an operand having address information next to the instruction code. An instruction discriminator for discriminating and a branch instruction detection signal from the instruction discriminator, and by the next execution cycle by the instruction selecting means, transmits the address information of the branch instruction to the instruction selecting means and branches. It is characterized by including an instruction fetch controller 20 for executing an instruction from the previous address, and it is possible to obtain a parallel processing processor whose processing efficiency is improved more than ever before.
It has a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel processor in one embodiment of the present invention, FIG. 2 is a timing chart of the main part of FIG. 1, and FIG. 3 is a block diagram of a parallel processor in another embodiment of the present invention. , FIG. 4 is a timing chart of the main part of FIG. 1 ... Instruction ROM, 2 ... First programmable counter, 3 ... Second programmable counter, 8 ... Timing generator, 16 ... ALU, 18 ... Context controller, 20 ... Instruction fetch controller.

Claims (1)

[Claims] 1. A program storage means for storing a program consisting of a group of instructions to be sequentially executed, and at least a first one for designating an address to the program storage means and selecting an instruction stored at the address.
And a second instruction selecting means, a computing means for performing a data operation based on the instruction sent from the program storing means, a timing generator for generating an instruction execution cycle, and a first instruction selecting means. Instructing the instruction to be selected by the second instruction selecting means after the instruction is selected,
A context controller that alternately allocates the execution cycles of the instructions selected by these instruction selection means, and an instruction selected by one instruction selection means is a branch instruction with an operand having address information next to the instruction code. An instruction discriminator for discriminating whether or not there is a branch instruction detection signal from the instruction discriminator and transmitting the address information of the branch instruction to the instruction selection means by the next execution cycle by the instruction selection means. And a parallel processing processor including an instruction fetch controller for executing an instruction from a branch destination address.