JPH0775307B2 - Narrow pulse width detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a narrow pulse width detection circuit, and more particularly to a circuit suitable for a glitch trigger of a digital oscilloscope.

(Prior Art) A digital circuit may malfunction according to an unnecessary narrow pulse generated due to a timing error or noise. That is, it is necessary to detect such a narrow pulse in order to investigate the cause of malfunction of the digital circuit.

FIG. 3 is a configuration explanatory view showing an example of such a conventional narrow pulse width detection circuit. In FIG. 3 (A), the pulse input signal IN is a direct one-shot multivibrator 1
Is input to the clock terminal of the D-type flip-flop 3 via the inverter 2. The output Q of the one-shot multivibrator 1 is input to the data terminal D of the D-type flip-flop 3.

FIG. 3B is a timing chart showing the operation of such a circuit. The one-shot multivibrator 1 outputs a pulse having a constant width Tw in synchronization with the rising edge of the pulse input signal IN. If the pulse input IN is wider than this pulse width Tw, the output OUT of the D-type flip-flop 3 remains L level, but if it is narrower than Tw, the D-type flip-flop 3 latches the output Q of the one-shot multivibrator 2. Then, its output OUT changes to H level. As a result, only pulses narrower than the predetermined width Tw can be detected.

FIG. 4 is another conventional circuit diagram. In (A),
Reference numeral 4 is an oscillator which outputs a pulse having a predetermined cycle only when the pulse input signal IN is at H level. The output of the oscillator 4 is input to the clock terminal of the down counter 5 and counted down. On the other hand, the inverted signal of the pulse input signal IN is input to the load terminal L of the down counter 5, and the set value is set at the rising edge of the pulse input signal. When the down counter 5 is down-counted and its output becomes zero, the terminal count signal TC becomes L level. This TC is detected by the D flip-flop 6.

As shown in the timing chart of (B), when the pulse width of the pulse input signal is wide, TC becomes L level and the output OUT of the D-type flip-flop 6 becomes L level. Like when the pulse width is narrow
Output of D-type flip-flop 6 without TC becoming L level
OUT goes high. As a result, only narrow pulses can be detected.

(Problems to be Solved by the Invention) However, according to the former configuration, the output pulse width Tw of the one-shot multivibrator 1 changes depending on the values of the capacitor C and the resistance R, so that the temperature, the humidity, or the secular change may occur. There is a drawback that Tw varies and cannot be accurately detected. Further, in order to change Tw, it is necessary to change the values of the capacitor C and the resistor R.

On the other hand, according to the latter configuration, the pulse width that can be detected can be changed by changing the set value input to the down counter 5, but the frequency of the output OSC of the oscillator 4 must be increased for accurate measurement. However, there is a drawback that manufacturing adjustment becomes difficult.

The present invention focuses on these points, and an object thereof is to provide a narrow pulse width detection circuit capable of accurately detecting a pulse having a narrow pulse width with a relatively simple configuration.

(Means for Solving Problems) The present invention relates to a delay element to which a pulse input signal is applied, a first D-type flip-flop to which a pulse input signal is applied to a clock terminal via the delay element, and a clock terminal. A second D-type flip-flop to which the pulse input signal is directly applied, and an exclusive OR gate to which the non-inverted output signals of these D-type flip-flops are added, and the inverted output signal of the first D-type flip-flop is The non-inverted output signal of the second D-type flip-flop applied to the data terminal of the second D-type flip-flop is applied to the data terminal of the first D-type flip-flop, the front end of the pulse input signal and the delay. A comparison time generation unit for outputting a comparison time signal equal to the time width of the front end of the output signal of the element, the pulse input signal and the comparison time generation unit And a pulse detector for detecting the output of the comparison time generator at the rear end of the pulse input signal.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a structural explanatory view showing an embodiment of the present invention. In FIG. 1, 10 is a delay element, which is a pulse input signal IN
Is added. The delay element 10 can change the delay time according to the data given from the outside. Reference numeral 11 is a comparison time generation unit, which is two D-type flip-flops 111 and 11
2 and an exclusive OR gate 113. The output signal of the delay element 10 is applied to the clock terminal of the D-type flip-flop 111, the non-inverting output Q of the D-type flip-flop 112 is applied to the data terminal D, and the non-inverting output Q is one of the exclusive OR gates 113. And the inverted output Q'is applied to the data terminal D of the D-type flip-flop 112. The pulse input signal IN is directly applied to the clock terminal of the D flip-flop 112, and the non-inverted output Q
Is also applied to the other input terminal of exclusive OR gate 113. Reference numeral 12 is a narrow pulse detection unit, which is composed of a D-type flip-flop 121, a delay element 122, and an inverter 123. The output signal of the exclusive OR gate 113 is applied to the data terminal D of the D flip-flop 121, and the non-inverted output Q is taken out as the output signal OUT. The pulse input signal IN is applied to the delay element 122, and the output signal of the delay element 122 is inverted by the inverter 123 and applied to the clock terminal of the D-type flip-flop 121.

The operation of the circuit thus configured will be described with reference to the timing chart of FIG.

In the initial state, each D-type flip-flop 111, 112 and 1
It is assumed that 21 has been reset and the Q output is at L level. When the pulse input signal IN rises at the time, this pulse input signal IN becomes D-type flip-flop 112.
It is directly applied to the clock terminal of. On the other hand, the pulse input signal IN is added to the clock terminal of the D flip-flop 111 at the time delayed by the time Td by the delay element 10. Further, the Q output of the D-type flip-flop 112 is applied to the data terminal D of the D-type flip-flop 111, and the Q ′ output of the D-type flip-flop 111 is the D-type flip-flop 1.
Twelve data terminals D are added. As a result, the D-type flip-flop 112 is triggered by the rising edge of the pulse input signal IN, its Q output is inverted, and the D-type flip-flop 112 is inverted.
111 is triggered by the rising of the output signal DL of the delay element 10 after the Q output of the D-type flip-flop 112 is inverted, and its Q output is inverted. After that, such an operation is repeated.
The Q outputs of these D-type flip-flops 111 and 112 are added to the exclusive OR gate 113. As a result, the exclusive OR gate 113 outputs the comparison time signal FT synchronized with the pulse input signal IN. In this way, the pulse width of the comparison time signal FT output from the exclusive OR gate 113 is equal to the delay time Td set in the delay element 10, and can be arbitrarily changed as described above.

On the other hand, the pulse input signal IN is compensated for the delay amount of the D-type flip-flops 111 and 112 and the exclusive OR gate 113 which form the comparison time generation unit 11 by the delay element 122 (the delay amount is zero in FIG. 2). , And is applied as a clock input EG to the clock terminal of the D-type flip-flop 121 via the inverter 123. Therefore, the D flip-flop 121 samples the comparison time signal FT in synchronization with the fall of the pulse input signal IN at time. Here, since the pulse width T ₁ of the pulse input signal IN from time to time is longer than the delay time Td set in the delay element 10, the Q output of the D-type flip-flop 121 remains L level and the output OUT is It is kept at L level. On the other hand, when the pulse width T ₂ of the pulse input signal IN becomes shorter than the delay time Td set in the delay element 10 as shown from time to time, the comparison time signal FT becomes the pulse input signal as shown from time to time. The H level becomes longer than the pulse width T _{2 of} IN, and the D-type flip-flop 121 samples the H level comparison time signal FT at the rising edge of the clock input EG at time. As a result, the Q output is inverted to the H level, the output OUT also becomes the H level, and only the pulse width of the pulse input signal IN that is shorter than the set delay time Td of the delay element 10 can be detected. Further, since the delay element is generally a distributed constant element, it is less susceptible to the influence of ambient temperature, and there is an effect that the upper limit of the detected pulse width becomes stable.

Although the delay element 10 having a variable delay time is used in the above embodiment, a fixed delay time may be used when the upper limit pulse width to be detected is fixed.

Further, in the above-mentioned embodiment, the positive pulse of the pulse input signal IN is focused, but when the negative pulse is desired, the pulse input signal IN may be input through the inverter.

(Effect of the Invention) As described above, according to the present invention, it is possible to realize a narrow pulse width detection circuit capable of accurately detecting a pulse having a narrow pulse width with a relatively simple configuration, and the practical effect is great.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIGS. 3 and 4 are explanations of a conventional narrow pulse width detection circuit. It is a figure. 10,122 …… Delay element, 11 …… Comparison time generator, 111,112,
121 ... D flip-flop, 113 ... exclusive OR gate, 12 ... narrow pulse detector, 123 ... inverter.

Claims (1)

[Claims] 1. A delay element to which a pulse input signal is applied, a first D-type flip-flop to which a pulse input signal is applied to a clock terminal through the delay element, and a pulse input signal which is directly applied to a clock terminal. 2 D-type flip-flops and an exclusive OR gate to which the non-inverted output signals of these D-type flip-flops are added. The inverted output signal of the first D-type flip-flop is the data of the second D-type flip-flop. The non-inverted output signal of the second D-type flip-flop applied to the terminal is applied to the data terminal of the first D-type flip-flop, and the time width between the front end of the pulse input signal and the front end of the output signal of the delay element is applied. A comparison time generation unit for outputting a comparison time signal equal to the pulse input signal and an output signal of the comparison time generation unit, Pulse detecting unit for detecting an output of the comparison time generating unit at the rear end of the input signal, the narrow pulse width detection circuit, characterized by comprising the city.