JPH0775315B2 - Buffer circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a high speed logic LSI.
The present invention relates to an LSI circuit suitable for the buffer circuit of.

BACKGROUND OF THE INVENTION The conventional buffer circuit is a so-called flip-flop type circuit in which an output signal is fed back to an input side circuit as seen in Japanese Patent Laid-Open No. 57-113483. For this reason, as the operating speed is not sufficient and the power consumption is large when switching signals, the performance is insufficient as a high-speed, low-power consumption circuit.

[Object of the Invention]

It is an object of the present invention to provide a logic LSI equipped with a high speed input / output buffer circuit.

[Outline of Invention]

A basic gate circuit and an input / output buffer circuit are manufactured on an LSI, and by combining and connecting these circuits, a logic LSI required by the user is manufactured.
There is an array master slice LSI. The average delay time per gate of the logic LSI manufactured by this LSI is the value obtained by adding the delay time of the internal circuit to the delay time of the output surface buffer circuit and dividing this by the number of logic stages.

When the number of logic stages of the internal circuit in the master slice LSI is small, there are a few logic circuits, and the average value is about 5 logic circuits. When the number of logic stages is small as described above, even if the internal gate circuit operates fast, the average delay time becomes large due to the delay of the input / output buffer circuit, and a high-speed logic LSI cannot be obtained.

The present invention has been made to reduce the influence of the delay time of the input / output circuit, and is characterized in that the input buffer and the output buffer circuits are also provided with a logical function.

Circuits that have logical functions in the input / output buffer circuit as described above are used in bipolar ECL master slices, but in CMOS and BiCMOS gate array master slice LSIs, the input / output buffer circuits have logical functions. Absent.
This is not only a circuit in which the input / output buffer circuit is hard to have a logical function, but also has a large number of internal logic stages and a logic circuit which is less affected by the delay time of the input / output buffer circuit as an application field.

However, as described above, the number of internal logic stages of the bipolar ECL master slice is small, and it is difficult to achieve high integration and high speed due to the constraints of power consumption and device yield. Currently, application of CMOS or BiCMOS circuit to this field is difficult. Is strongly demanded. As described above, circuits with a very small number of logic stages are often used in circuits in such application fields, and it is essential to reduce the influence of the delay time of the input / output buffer circuit in order to manufacture high-speed logic LSIs. is there.

In the application field of bipolar ECL master slice LSI, ECL input / output level is commonly used because ultra high speed operation is required, and it is also a necessary condition that the input / output buffer circuit can support this signal level.

The present invention has been made to meet such requirements. Basically, a MOSFET is connected to the base electrode of a switching transistor of a current switching circuit used in a bipolar ECL logic LSI, and the gate of the MOSFET is connected to the base electrode of the switching transistor. Add a signal with a large amplitude of TTL level or higher, and if necessary,
By supplying the ECL level signal directly to the base electrode of the switching transistor, it is to provide an input / output buffer circuit capable of supporting both the ECL and TTL signal levels.

Example of Invention

 A detailed description will be given below based on this embodiment.

FIG. 1 shows an input buffer circuit according to the present invention. Between the collector and base of the input bipolar transistor, based on the current switch circuit consisting of the reference transistor QA5 to which the ECL reference voltage V _BB used in the bipolar ECL master slice is applied to the base and a plurality of input transistors QA2, QA3, QA4, PMOS and NMOS respectively between the base and the power supply V _T
Is a circuit to which is added. In the input buffer circuit, the ECL signal is input to at least one input.
Connected to 11. Output OA of current switch, ▲
Since ▼ is supplied to the BiCMOS or CMOS circuit, it is desirable that its amplitude is large. Therefore, it is supplied to the input transistor QA2 after being level-shifted by the bipolar transistor QA1 and the diode-connected bipolar transistor DA1. The second input is BiCMOS or CMO
When it is a large amplitude signal from the S circuit, it is supplied to A21,
Supply current to the base terminal A2 of input transistor QA3
To operate. It goes without saying that, when the second input is at the ECL level, the level shift is performed by the device corresponding to the bipolar transistor QA1 and the diode DA1 as in the first input, and then directly connected to the terminal A2. The third input signal is similar to the second input, but if there is no third input, MOSFET is not connected and A3 is set to QA.
All you have to do is connect it to the 4 Emitter terminal. The other operations are the same as or very similar to those of the ECL bipolar logic circuit, so the description thereof will be omitted.

According to this circuit, when both ECL and TTL signals are input, OR and NOR are output to the output terminals, respectively, and it goes without saying that a logic circuit can be configured by this. The delay time of this circuit was 3.2 ns, and the increase of the delay time was small compared with 3 ns of the input buffer circuit which has no logic function.

FIG. 2 shows the output buffer circuit of the second embodiment. Basically, it is the same as the input buffer circuit shown in FIG.
However, for all the input bipolar transistors, MOSFETs are provided to support both ECL and TTL signals, and the base of the direct input transistor is not changed for ECL input without level shifting. All you have to do is connect it to the terminal.

The delay time in this circuit was almost the same as the delay time in the ECL circuit, and it was possible to effectively reduce the delay time in the output buffer circuit by giving the output circuit a logical function.

In the embodiment shown in FIGS. 1 and 2, the source terminal of the NMOS FET is connected to the power supply V _T , but this terminal should be connected to the emitter terminal of the input bipolar transistor.
It is also possible to connect to _EE . When making the former connection, it is desirable to make the gate width of the NMOS / FET wider than in the circuit of FIG. 1, and conversely, when making the latter connection. A characteristic of these connections is that the former connection method has a small device layout and the occupied area for connection, and there is almost no difference in the occupied area between the embodiment (FIGS. 1 and 2) and the latter connection method. The delay time of the circuit was the smallest in the latter connection method in which the source terminal of the NMOSFET was connected to the power supply V _EE .

In addition, the source terminal of the PMOSFET is connected to the collector terminals A6 and B6 of the bipolar transistor in FIGS. 1 and 2, but a second power supply is connected to this and the second power supply voltage is input to the ECL input. It is also possible to set the high potential level corresponding to the signal. This reduces the amount of change in the potentials of the terminals A11 and B11 due to the input signal, and has the effect of realizing a faster circuit.

FIG. 3 shows an output buffer circuit shown in the third embodiment.
It is basically the same as the output buffer circuit shown in FIG. However, in FIG. 2, the conduction / non-conduction of the input bipolar transistor is controlled by the input of the MOSFET, but in this embodiment, the ECL input signal is directly connected to the base terminal of the bipolar transistor, and a large amplitude signal It is characterized in that the input is directly input to the gate of the NMOSFET, and the logic function is provided by the conduction / non-conduction of this MOSFET.
In Figure 3, NMOSFET MC11, MC21, MC31 was used.
It can be a PMOSFET or mixed. The reason why a MOS transistor receives a signal of large amplitude is as follows. If a signal with a large amplitude is received by the bipolar transistor instead of the MOS transistor, the load RC1 is applied to the collector of the bipolar transistor.
Is connected, a reverse bias is applied between the base and collector. Then, there is a risk that the bipolar transistor will be saturated and latch up will occur. Therefore, a signal of large amplitude must be received by the MOS transistor.

〔The invention's effect〕

As described above, according to the present invention, the delay time of the conventional input buffer circuit and the output buffer circuit is added to the delay time of the internal logic circuit to increase the substantial delay time. Is added, and the input signal level is compatible with both ECL and TTL signals, the substantial delay time of BiCMOS and CMOS logic LSI is reduced, and high-speed operation comparable to bipolar ECL logic LSI is further improved. It was possible to realize it with low power consumption.

[Brief description of drawings]

FIGS. 1 and 2 are input buffers according to the present invention capable of handling input signals having both ECL and TTL signal levels,
FIG. 3 is a circuit diagram showing an output buffer circuit, and FIG. 3 is a diagram showing another output buffer circuit according to the present invention. QA1, ..., QA6, QB1, ..., QB7, QC1, ..., QC7 ... bipolar transistors, RA1, ..., RA3, RB1, ..., RB5, RC1, ..., RC4 ... resistors.

Claims (2)

[Claims] 1. A first bipolar transistor having a base to which a reference voltage is applied, and a first bipolar transistor having one end connected to a collector of the first bipolar transistor and the other end connected to a first potential. A load, a constant current circuit connected to the emitter of the first bipolar transistor, a second bipolar transistor having its emitter connected to the emitter of the first bipolar transistor, and a collector of the second bipolar transistor A second load whose one end is connected to the other end and whose other end is connected to the first potential, and a MOS transistor whose source / drain path is formed between the emitter / collector of the second bipolar transistor. The gate of the MOS transistor has a first potential having a second potential and a third potential as input levels. Input signal is applied, the base of the second bipolar transistor is the first
A second input signal having a signal amplitude smaller than that of the input signal is applied. 2. The buffer circuit according to claim 1, wherein the first and second bipolar transistors are NPN type transistors, and the MOS transistors are N channel type transistors.