JPH077598B2 - DC magnetic flux parametron memory circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a DC magnetic flux parametron memory circuit using a Josephson device.

[Background of the Invention]

Switching circuits using the Josephson device are well known in the art, and are represented by quantum interference circuits, direct connection circuits, and the like. These circuits are based on the IBM Journal of Rese
arch and Development) Volume 24, No.2 (1980) 130-1
See page 42 for details. Switching circuits using these Josephson devices according to the prior art have a drawback that the circuit gain is small and a negation circuit cannot be formed. Further, the power consumption of these circuits is 1 to 10 μW, which is not a small value compared with the heat of vaporization of liquid helium, and it is difficult to make a large-scale logic integrated circuit or memory integrated circuit, and thus a large-scale computer system.

As a circuit with high gain and low power consumption, DC Flux Parametron (DCFP) is used to avoid the shortcomings of the circuits using these conventional Josephson devices.
There is a circuit). The principle of the DCFP circuit is described in detail in Goto et al., RIKEN symposium "Josephson Electronics", Proceedings (hereinafter simply referred to as literature) (March 16, 1984), pages 1 to 3. . DC
For an example of applying the FP circuit to a memory circuit, see the above-mentioned pages 96-
It is described on page 102. In the prior art of the DCFP circuit, although the principle operation of the memory cell has been studied, the structure of the memory system using those memory cells is not mentioned.

[Object of the Invention]

An object of the present invention is to read data using a DCFP circuit,
Another object is to provide a writable random-access DC magnetic flux parametron memory.

[Outline of Invention]

In order to achieve this object, in the present invention, memory cells using a DCFP circuit are arranged in a matrix, and two selection lines common to the row direction and the column direction are magnetically coupled to the excitation inductor of each memory cell, A common data line connected to each memory cell is arranged, and an amplifier circuit connected to the data line is arranged.

Example of Invention

The present invention will be described below with reference to examples. FIG. 1 is a principle configuration diagram of a memory cell using a DCFP circuit. This memory cell is composed of a DCFP circuit including a series connection loop of two Josephson junction devices 20a and 20b and inductors 21a and 21b, and a quantum interference circuit 12 in which the Josephson junction device 10 and the inductor 11 are connected in series.

The quantum interference circuit 12 has a phase line 13 whose electron wave phase corresponds to π.
Connected to. As a result, the storage operation is performed through the magnetic flux. The stored information can be discriminated by the directions a and b of the current flowing out of the quantum interference circuit 12. For details of the quantum interference circuit, refer to page 99 of the reference document.

The DCFP circuit serves as a sense amplifier for the quantum interference circuit. When currents in the direction of C are applied to the row and column address lines 32 and 33, respectively, when the current from the quantum interference circuit 200 is in the direction of A, the current flowing through the Josephson junction device 20b increases and enters a voltage state. On the other hand, when the current from the quantum interference circuit 12 is in the direction of B, the current flowing through the Josephson junction device 20a increases and enters the voltage state. As a result, a large current excited by the currents in the row and column address lines 32 and 33 flows in the direction a or the direction b.

In order to read data from this memory cell, an address current is passed through the two address lines in the matrix. This address current becomes an excitation current, and the data in the memory cell appears as a current in the load inductor 15. Sufficient read output cannot be obtained by passing the current through only one address line in the row or column. To write data in this memory cell, the write current is supplied to the memory cell via the load inductor 15 by interrupting the address currents of the two address lines in the matrix. When a current is passed through even one address line in a row or column, the memory cell is locked and the data does not change.

To retain data in this memory cell, there are two methods of cutting off all address currents or keeping all address currents flowing.

FIG. 2 is a DC magnetic flux parametron memory circuit according to the first embodiment of the present invention. In this embodiment, a memory cell 100a, 100b, 100c, 10 shown in FIG. 1 using a DCFP circuit is used.
0d are arranged in a matrix, and the other end of the quantum interference circuit of each memory cell is connected to the electron wave phase lines 108a and 108b.
The phases of the electron wave phase lines 108a and 108b are supplied via the terminal 107. Each memory cell has a row address terminal 120a,
It is selected by the row address current flowing through the row address lines 121a and 121b through the 120b and the column address current flowing through the column address lines 111a and 111b through the column address terminals 110a and 110b. Load inductors 15a, 15b, 15c, 15d for each memory cell
Are coupled to coupling inductors 210a, 210b, 210c, 210c, and the coupling inductors are connected in series in the row address direction by the data lines 200a, 200b.
200a and 200b are connected to the input / output amplifier circuit 101 which is a DCFP circuit. The input / output amplifier circuit 101 is connected to the load inductor 104 and terminals.
105 is connected. The input / output amplifier circuit 101 is connected to the terminal 10
It is excited by an excitation current flowing through the excitation line 103 via 2. Next, the operation of this memory circuit will be described. In the read operation of the memory circuit, one of the row address lines 120a and 120b is used.
Similarly, one of the column address lines 110a and 110b is selected, and a row address current and a column address current are supplied to each.
The memory cell at the position where the selected row address line and column address line intersect is excited, and the data of the memory cell is transferred to the data line 200 via the load inductor 15 and the coupling inductor 210.
Is guided to the input / output amplifier circuit 101. The memory cells connected to only one of the row address line and the column address line selected here are in a half-selected state, and since these memory cells are not sufficiently selected, the data from the memory cells is not selected. Does not appear on the data lines 200a and 200b. Next, when an excitation current is applied to the excitation line 103 of the input / output amplifier circuit 101, the data read via the data line 200 is amplified, and a read / take current is applied to the load inductor 104. In the write operation, one of the row address lines 120a and 120b, and similarly one of the column address lines 110a and 110b is selected, and the row address current and the column address current are cut off, and the other row and column addresses are selected. Apply address current to all lines. In this state, only the address current of the memory cell at the intersection of the selected row address line and column address line is zero, and only this memory cell can write data. Next, if an excitation current is applied to the excitation line 103 of the input / output amplifier circuit 101, the input terminal
The input signal applied to 105 is increased so that data lines 200a, 2
Applied to 00b, data is written in the selected memory cell.

FIG. 3 shows a second embodiment according to the present invention. The same reference numerals as in FIG. 2 are attached. In the embodiment shown in FIG. 3, the coupled inductors 210a, 210b, 210 of the first embodiment shown in FIG.
memory cells 100a, 100b, 100c, 100 without going through c, 210d.
load inductors 15a, 15b, 15c, 15d of d
It is a configuration that is connected to a and 200b. It is apparent that the second embodiment having this configuration also performs the same memory operation as that of the first embodiment.

FIG. 4 shows a third embodiment according to the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals. In the embodiment shown in FIG. 4, each memory cell 100a of the second embodiment shown in FIG.
The cell amplifier circuits 400a, 400b, 400c, 400d using a DCFP circuit are further connected to the output terminals of 100b, 100c, 100d. Each cell amplifier circuit 400a, 400b, 400c, 400d has a terminal 401
It is excited by the excitation current flowing through the cell amplification line 402 via the. Cell amplification circuits 400a, 400b, 400 used in this embodiment
The c and 400d are placed in pairs in each memory cell and work so as to amplify the data that goes in and out of the memory cell and to perform stable memory operation.

FIG. 5 is an example of another memory cell 500 used in the memory circuit according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. The memory cell shown in FIG. 5 comprises a state switching line 51 instead of the address line of the memory cell shown in FIG. 1 and inductors 50a and 50b coupled to the inductors 21a and 21b connected thereto. In this memory cell, when a state switching current flows through the state switching line 51, the memory cell is excited and enters a memory data read state. When the state switching current does not flow in the state switching line, the state of writing data via the load inductor 15 is set. FIG. 6 shows a fourth embodiment according to the present invention. The same parts as those in FIGS. 2 and 5 are designated by the same reference numerals. In the embodiment shown in FIG. 6, the memory cells shown in FIG. 5 are arranged in a matrix, and address amplification circuits 510a, 510b, 510c, 510d by DCFP circuits are arranged in pairs in each memory cell 500a, 500b, 500c, 500d. It is a configuration. The state switching line 51 of each memory cell is tangentially connected in series, and the state switching current flowing through the state switching line 51 is 501.
Supplied by. Each address amplification circuit 510a, 510b, 510
Row address lines 121a and 121b and column address line 111 are included in c and 510d.
a and 111b are combined, one row address line and one column address line are selected, and an address current is passed through the selected address line to select one memory cell from one memory cell arranged in a matrix. Can be selected. The operation of the memory circuit shown in FIG. 6 will be described below. In the read operation of the memory circuit, first, a state switching current is passed through the state switching line 51 to bring all the memory cells into the reading state. Then select the memory cell using the address line,
The address amplification circuit 510 is excited. The data of the memory cell amplified by the address amplification circuit 510 is guided to the input / output amplification circuit 101 by the data line 200 and amplified.
In the write operation of the memory circuit, the state switching current does not flow,
All memory cells are in the written state. Next, the input / output amplifier circuit 101 is excited to amplify the signal at the input terminal 105 and send it to the data line 200. Next, a memory cell is selected using the address line, the address amplification circuit 510 is excited, and the signal sent to the data line 200 is written in the memory cell. Data maintenance can be performed with or without the switching current.

〔The invention's effect〕

As described above, according to the present invention, a random-access DC magnetic flux parametron memory circuit using a DCFP circuit can be constructed. Since the DC magnetic flux parametron memory circuit using the DCFP circuit operates at high speed with low power consumption,
A high-speed memory circuit can be configured, which is effective in improving the performance of the computer.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional memory cell using a DCFP circuit,
2 is a diagram showing a first embodiment of the memory circuit according to the present invention, FIG. 3 is a diagram showing a second embodiment of the memory circuit according to the present invention, and FIG. 4 is a third diagram of the memory circuit according to the present invention. FIG. 5 is a diagram showing another embodiment of the memory circuit according to the present invention, and FIG. 6 is a diagram showing a fourth embodiment of the memory circuit according to the present invention. 100 ... Memory cell, 15 ... Memory cell load inductor, 101 ... Input / output amplifier circuit, 102 ... Input terminal, 103 ...
… Excitation line, 104 …… Load inductor, 105 …… Input terminal,
107 …… phase terminal, 108 …… red line, 111 …… Y address line, 121 …… X address line, 200 …… data line, 210 ……
Coupling inductor, 400 ... bit amplification circuit, 500 ... memory cell, 51 ... status switching line, 510 ... address amplification circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichi Goto 2-1, Hirosawa, Wako-shi, Saitama RIKEN (72) Inventor Nobuo Miyamoto 1-280, Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Research Institute In-house

Claims (3)

[Claims] 1. An information storage section in which a first inductor and a first Josephson junction element are connected in series, and second and third information storage sections.
Of the inductor and the second and third Josephson junction elements are connected in a loop, and are connected to a connection node between the excitation unit connected to one terminal of the information storage unit and the second and third inductors. Fourth for reading and writing information
A plurality of row-direction selection lines magnetically coupled in common to the second and third inductors of the plurality of memory cells arranged in each row, respectively. A plurality of column direction selection lines magnetically coupled to the second and third inductors of the plurality of memory cells arranged in the column and a fourth inductor of the memory cells arranged in the matrix. A DC flux parametron memory circuit having a data line coupled to the. 2. The DC flux parametron memory circuit according to claim 1, wherein the plurality of fourth inductors are magnetically coupled in common to the data line. 3. The memory cell according to claim 1, wherein each of the memory cells has fifth and sixth inductors connected to the connection node, and fourth and fifth Josephson junction elements are connected to the fifth node. , A first circuit connected in series so as to form a loop with a sixth inductor, and a state switching line magnetically coupled in common to the fifth and sixth inductors, and a state of each memory cell A DC magnetic flux parametron memory circuit in which switching lines are connected in series and a current is passed when reading information from a memory cell.