JPH0776783B2 - Semiconductor device and output terminal test method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC circuit and a method of testing its output terminal.

2. Description of the Related Art Generally, in an IC circuit, when the I / O terminal part has an open drain structure, an external pull-up resistor must be connected to generate a high-level output voltage at the open drain. FIG. 5 shows such a conventional example. In the figure, an N-channel MOS transistor (21) is provided in the output circuit section of the IC (20), and one end of the output terminal (22) connected to the drain of this transistor (21) has an external power supply voltage V A resistor (23) connected to _DD2 (V _DD2 ≧ V _DD ) is provided. Now, connect a tester (not shown) to the output terminal (22) when testing the output terminal (22) to test whether the output of the transistor (21) normally changes according to the change of the input V _IN. Therefore, the pin capacitance (24) of the tester is added between the output terminal (22) and the ground point. The tester takes in and processes the voltage output to the output terminal (22) when an input signal is applied to the transistor (21). The taking-in is performed by sampling the output voltage.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, in the above-mentioned conventional example, the high-level voltage generated at the output terminal (22) falls due to the resistance division of the pull-up resistor (23) and the transistor (21) at the time of conduction. Due to the variation of (21) (thus the variation of resistance when the transistor is conductive), the high-level voltage falls as shown in FIG. 6 and the rollbell voltage also varies. Therefore, it becomes necessary to adjust the sampling timing setting and the low / high level determination level in the tester. Another one
As one problem, as shown in Fig. 7, the pull-up resistor (23) needs to be set to a large value in order to output a low level [by the resistance division of the transistor (21) and the pull-up resistor (23) To obtain a voltage], it takes time for the time constant of the resistor (23) and the capacitor (24) to output a high level. For this reason, it becomes necessary to adjust the sampling setting or resistance value in the tester depending on the operation speed. This means that the tester must be adjusted for each IC to be tested, and it has a drawback that it is unsuitable for the inspection process in mass production. In FIG. 7, SL shows the level at the time of the suppression. The rising and falling speed depends on the pull-up resistor (23),
The level SL is different between (a) and (b).

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor device and a test method that do not cause variations in the rising and falling of the output voltage generated at the output terminal.

Means for Solving the Problems In order to achieve the above-mentioned object, the test method of the present invention provides a normal use state between an N-channel or P-channel first MOS transistor and a P-channel or N-channel second MOS transistor. Is connected to a third MOS transistor to which a gate voltage is applied so that it is turned off and turned on during a test, and the first MOS transistor and the third MOS transistor are connected.
In an output circuit of a semiconductor device in which an output terminal is connected to a middle point of connection of a transistor, a tester is connected to the output terminal to output a test signal for turning on the third MOS transistor when the output terminal is tested. The circuit is operated as pseudo CMOS. Here, the pseudo CMOS means that only the power supply side is in conduction with the output terminal and the reference potential point side is not in conduction when outputting a high level as in the CMOS, and outputs a low level. In this case, the MOS transistor circuit is in a non-conduction state with the power supply side and in a conduction state with the reference potential point side.

Further, the semiconductor device of the present invention is provided with an N-channel or P-channel first device connected in series between the reference potential point and the power supply line.
1, a second MOS transistor, an output terminal connected to a connection midpoint of the first and second MOS transistors, a gate circuit connected to a gate of the second MOS transistor, a gate of the first MOS transistor and the gate circuit Means for conducting an input signal to a first input terminal of the gate circuit and means for conducting a test signal to a second input terminal of the gate circuit, wherein the second MOS transistor is turned off in a normal use state. The output circuit is simulated by applying a voltage and applying an inverted input signal as the gate voltage through the gate circuit so that ON and OFF are opposite to those of the first MOS transistor during testing. I am trying to operate it as CMOS.

According to the output terminal test method of the present invention, the output circuit of the semiconductor device operates as a pseudo CMOS during the test, so that the first MOS transistor is turned off by the input signal and the second MOS transistor is turned off.
The voltage at the output terminal rises when the transistor is ON, and falls when the first MOS transistor is ON and the second MOS transistor is OFF. Therefore, it is not necessary to connect the pull-up resistor to the output terminal at the time of the test as in the conventional case, and therefore the rise and fall of the output terminal voltage hardly occur.

Further, in the semiconductor device of the present invention, the second MOS transistor is turned off when there is no test signal, but when there is a test signal, the second MOS transistor is turned on and off by the input signal.
The second MOS transistor is ON and the first M
A high level can be generated at the output terminal by turning off the OS transistor, and a voltage at the output terminal can be lowered by turning off the second MOS transistor and turning on the first MOS transistor. Therefore, also in this case, it is not necessary to connect the pull-up resistor to the output terminal during the test.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an output circuit of an IC (4) for implementing the test method of the present invention. In the same figure, (1) and (2) are the first and second parts connected in series in the CMOS structure between the ground point and the power supply line (5).
It is a MOS transistor, and (3) is a third MOS transistor connected between them. In the present embodiment, the first MOS transistor (1) and the third MOS transistor (3) are configured as N-channel type MOS transistors, but not necessarily limited thereto.
The MOS transistor (2) is a P-channel type MOS transistor. The output terminal (7) is provided at the connection midpoint (6) of the first and third OMS transistors (1) and (3).
Are connected. The third MOS transistor (3) can be configured as an enhancement type or a depletion type by the mask option of the portion (8) shown by the dotted line. In other words, if this output circuit makes the third MOS transistor (3) conductive by the mask option, C
It becomes a MOS circuit and becomes an open drain by making the third MOS transistor (3) non-conductive. In both cases, the gate of the third MOS transistor (3) is connected to the ground point in the normal use state.

Now, it is assumed that this output circuit is configured to be an open drain in a normal use state by a mask option. Therefore, when the voltage output from the output circuit is taken into a tester (not shown) to test the output terminal (7), the third terminal is used in the same manner as in the normal use state.
If the gate of the MOS transistor (3) is connected, the output terminal (7) pull-up resistor must be connected for testing as described in the conventional example. When a test signal (high level voltage in this case) is applied, the third MOS transistor (3) becomes conductive, and this output circuit operates as a pseudo CMOS.

FIG. 2 shows the input voltage (V _IN ) and the voltage (V _OUT ) generated at the output terminal (7) in such a case. In this case, there is no variation in the rise and fall of the output voltage generated at the output terminal (7) by the pseudo CMOS. However, the upper limit of the output voltage (V _OUT ) is lower than the voltage (V _DD ) of the power supply line (5) by the threshold voltage of the third MOS transistor (3). In FIG. 2, GND indicates the potential at the ground point.

FIG. 3 is a structural diagram of a semiconductor device which constitutes the output circuit of FIG. 1, and shows the first MOS in the P-type semiconductor substrate (9).
A transistor (1), a second MOS transistor (2) and a third MOS transistor (3) are formed as shown. Here, P indicates a P-type region and N indicates an N-type region. Further, (10) is an input terminal and (11) is a test terminal. In this case, since the third MOS transistor (3) is turned off in the normal use state, even if a voltage higher than the power supply voltage (V _DD ) is applied from the outside, the first MOS transistor (1) Since no forward voltage diode exists in the third MOS transistor (3), a high breakdown voltage open drain can be formed.

Next, FIG. 4 shows an embodiment of the semiconductor device of the present invention, in which the first MOS transistor (12) and the second MOS transistor (13) are connected in cascade between the ground point and the power supply line (5). Where the first and second MOS transistors (12) (13)
Is not particularly limited to this, but N channel type MO
It is configured as an S transistor. The output terminal (14) of the NOR gate (14) is connected to the gate of the second MOS transistor (13).
c) is connected to the first input terminal (14) of this NOR gate (14).
An input signal is applied to a), and a voltage (hereinafter, also referred to as a test signal) obtained by inverting a test signal (high level) is applied to the second input end (14b).

Therefore, in this circuit, the second MOS transistor (13) is OFF and the open drain is formed only by the first MOS transistor (12) in normal use. However, when the test signal is applied, the second MOS transistor (13) is input. ON / OFF control is performed according to the voltage (V _IN ). Therefore, when making the output terminal (7) high level during the test, if the low level is given as the input voltage (V _IN ), the first MOS
The transistor (12) is OFF, the second MOS transistor (13) is
It is turned on and the output terminal (7) can be set to high level. Next, to set the output terminal (7) to a low level, a high level may be given as the input voltage (V _IN ).

According to the test method of the present invention, the open-drain output circuit operates as a pseudo CMOS in the test mode, so that it is not necessary to connect a pull-up resistor to the output terminal and the voltage of the output terminal rises and falls. Since there is no variation, it is not necessary to adjust the sampling timing of the tester connected to the output terminal for each semiconductor device product, which is particularly suitable for the inspection of the output terminal in the semiconductor device production process.

In addition, since the semiconductor device of the present invention is provided with a gate circuit for changing the configuration of the output circuit according to the test signal so that the output terminal can be made high in level by the configuration of the output circuit itself, When testing the output terminals, there is no variation in the rise and fall of the output voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit portion in a semiconductor device for carrying out the test method of the present invention, FIG. 2 is a signal waveform diagram thereof, and FIG. 3 is a structural diagram. FIG. 4 is a circuit diagram showing an output circuit portion in another semiconductor device according to the test method of the present invention. FIG. 5 is a circuit diagram of a conventional example, and FIG. 6 is a diagram showing a voltage waveform at its output terminal. FIG. 7 is a diagram showing the relationship between the test speed and the judgment voltage level at the time of sampling in the circuit of the conventional example. (1) ... first MOS transistor, (2) ... second MOS transistor, (3) ... third MOS transistor, (5) ... power supply line, (6) ... connection midpoint, (7) …… Output terminal, (12) …… First MOS transistor, (13) …… Second MOS transistor, (14) …… Gate circuit, (GND) …… Reference voltage, (V _DD ) …… Supply voltage , (V _DD2 ) ... External power supply voltage.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 21/8238 27/04 27/092 H01L 27/04 T 9170-4M 27/08 321 L

Claims (2)

[Claims] 1. A first MO of N-channel or P-channel
S-transistor and P-channel or N-channel second
A third MO that is given a gate voltage between the MOS transistors so that it is turned off in normal use and turned on during testing.
In an output circuit of a semiconductor device in which an S transistor is connected and an output terminal is connected to a connection midpoint between the first MOS transistor and the third MOS transistor, a tester is connected to the output terminal to test the output terminal. A method for testing an output terminal of a semiconductor device, wherein the output circuit is operated as a pseudo CMOS by applying a test signal for turning on the third MOS transistor at the time. 2. An N-channel or P-channel first and second MOS transistors connected in series between a reference potential point and a power supply line, and a connection midpoint between the first and second MOS transistors. An output terminal, a gate circuit connected to the gate of the second MOS transistor, and the first MO
The second MO transistor comprises means for conducting an input signal to the gate of the S-transistor and the first input terminal of the gate circuit, and means for conducting a test signal to the second input terminal of the gate circuit.
The gate voltage is applied to the S-transistor so that it turns off in the normal use state, and the input signal inverted through the gate circuit is applied as the gate voltage so that it turns on and off in reverse to the first MOS transistor during the test. A semiconductor device characterized by being provided.