JPH0776945B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an address translator and a buffer memory (hereinafter,
The present invention relates to an information processing device having a cache device).

[Conventional technology]

FIG. 3 is a block diagram showing a conventional information processing apparatus having a cache device. In the figure, (1) is a memory address register, and (2) is a memory address register (1) a held logical address is a real address. (3) is a real address register that holds the real address translated by the address translator (2), and (4) is a cache device that holds the contents of a main memory (not shown). , (5) is an index array included in the cache device (4), (6) is a data array included in the cache device (4), (7)
A first comparator for comparing the contents of the real address register (3) and the index array (5), (8) a second comparator, and (9) a first and a second comparator (7). ) And (8), and a control circuit for controlling the reading of data from the data array (6), (10)
The data array (6) based on the output of the control circuit (9)
Is a selector for selectively reading out the contents of.

Next, the operation will be described. In the following explanation,
The address before the address translation is called a logical address, and the address after the address translation is called a real address. In general, the upper l bits of a logical address of l + m bits are subjected to address conversion to obtain a value of n bits, and the lower m bits of the logical address are added to this value to obtain n.
A + m-bit real address is obtained. That is, the value of the lower m bits of the logical address and the value of the lower m bits of the real address are the same (l, m, and n are natural numbers).

In FIG. 3, the cache device (4) is composed of an index array (5) and a data array (6), and the index array (5) determines whether necessary data exists in the data array (6). Used to find out. The data held in the index array (5) is the value of the real address where the data in the corresponding data array (6) is located on the main memory (not shown). The data array (6) holds the data retrieved from the main storage device.

First, the lower m bits of the memory address register (1) are sent to the address signal line CACADR of the cache device (4), and the upper l bits are sent to the input signal line PGADR of the address conversion device (2). The address translation device (2) has a function of translating a logical address into a real address. That is, based on the value of the input signal PGADR that is a logical address, processing such as table search is performed, and as a result, an output signal that is a real address is generated. The output signal of the address translation device (2) is set in the real address register (3) via the signal line RLADR. Whether the necessary data exists in the cache device (4) is determined by the contents of the real address register (3) and the output data of the index array (5) read from the address output to the signal line CACADR. , The first comparator (7) and the second comparator (8) are used for comparison. That is, if the output of either the comparator (7) or (8) indicates a match, the required data is present in the data array (6), and the selector is controlled by the control circuit (9). Data is retrieved via (10). If, on the other hand, the outputs of both comparators (7) and (8) show a mismatch, then the required data is not present in the data array (6) and the data is issued by the main memory by issuing a memory request. Will be taken out.

FIG. 4 shows a series of operations of the conventional information processing apparatus configured as shown in FIG. In step (11) of FIG. 4, when the address of the required data is set in the memory address register (1), the address conversion in step (12) and the setting of the real address register (3) in step (13) are performed. And the cache device (4) is accessed in step (14) at the same time. Next, in step (15), the contents of the index array (5) and the contents of the real address register (3) are compared to check whether or not there is necessary data in the cache device (4). If the comparison results do not match, the necessary data is fetched from the main memory in step (16). On the other hand, if the comparison result is a match, the necessary data is fetched from the cache device (4) in step (17).

[Problems to be solved by the invention]

Since the conventional information processing device is configured as described above, when a plurality of cache devices are provided, it is necessary to provide the same number of address translation devices as the cache devices, which increases the amount of hardware. There was a point.

The present invention has been made to solve the above problems, and an object thereof is to obtain an information processing apparatus that does not require all of the plurality of cache devices to have an address conversion function.

Another object of the present invention is, in addition to the above object, an information which minimizes a decrease in processing speed that may occur when some of the cache devices are not provided with an address translation function. The purpose is to obtain a processing device.

[Means for solving problems]

The information processing apparatus according to the present invention is provided with a real address register for holding a result of address translation performed by an external address translation device and a validity instruction flag thereof in a cache device that does not have address translation means.

Further, an information processing apparatus according to another invention of the present invention detects that the address boundary of a data address from which data is currently being fetched is different from the address boundary of a data address from which data was previously fetched, in the above. A detection means is added, and when the detection means detects that the address boundaries are different, the memory request is output.

[Action]

The real address register and the valid indication flag according to the present invention, when fetching data from the cache device,
Used to compare with the real address data read from the index array to see if the required data is in the cache device.

Further, according to another invention of the present invention, the address boundary of the data address from which the current data is to be fetched is compared with the address boundary of the data address from which the previous data was fetched, and if these two address boundaries are different, it is unconditional. Issue a memory request to the external address translation device, check whether there is necessary data in the cache device after the address translation is completed by the external address translation device, and if the required data is in the cache device, invalidate the memory request and cache. The data is fetched from the device, and if the required data is not in the cache device, the memory request process is continued and the data is fetched from the main memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, (1) and (4) to (10) are the same as those in the conventional information processing apparatus shown in FIG. (18) is, when the information processing device issues a memory request, receives the contents of the memory address register (1) which holds the value of the logical address at that time via the signal line PGADR, and performs processing such as table search. Address conversion is performed and the resulting real address value is sent to the signal line RLADR.
The address conversion device (19) that outputs the above detects the state of the memory address register (1), compares the address boundary (higher 1 bit) with the address boundary of the previous data, and if they match, For example, the cache device (4) is accessed, and if they do not match, a data fetch request (requesting means) to the main memory device and an address translation device (18)
Send a memory request for requesting data reception via the signal line PGADR to the signal line MEMREQ, control the setting of the valid instruction flag (20) via the control signal line RABV, and control the signal line RABS. Control of the setting of the real address register (21) via the comparator (7)
(8) A detection control circuit that controls the memory request transmission continuation invalidation according to the comparison result of (detection means), and (20) a validity indicating whether the contents of the real address register (21) are valid or invalid. The instruction flag, (21), is a real address register that holds the value of the real address corresponding to the value of the memory address register (1).

The address translation device (18) has a function of performing address translation for a logical address sent from one or more other cache devices included in the information processing device and sending back a real address.

FIG. 2 shows a series of operations of the information processing apparatus configured as shown in FIG. 1 according to the present invention. In FIG. 2, the steps (11) and (14) to (17) are the same as those shown in FIG. In FIG. 2, step (2
In 2), the detection control circuit (19) compares the upper 1 bits of the currently set memory address with the upper 1 bits of the previously set memory address. If the comparison result is a match, the logical address currently set in the memory address register (1) is translated by the address translation device (18), and the real address value already exists in the real address register (21). Therefore, normal cache access will be performed. On the other hand, if the comparison result does not match, the logical address in the current memory address register (1) is translated by the address translation device (18), and the value of the real address is still stored in the real address register (21). Since it does not exist, the detection control circuit (19) unconditionally issues a memory request (requesting means). Hereinafter, each step in this case will be described.

In step (23), a memory request is unconditionally issued, and at this time, memory address register (1)
Since the correspondence between the logical address therein and the real address in the real address register (21) is incorrect, the valid instruction flag (20) is changed to the invalid state.

Next, in step (24), after address conversion, that is, after the real address corresponding to the logical address in the memory address register (1) is output onto the signal line RLADR, the signal line RLADR is sent to the real address register (21). Set the above data and change the valid indicator flag (20) to the valid state.

Then, in step (25), the cache device (4) is accessed based on the contents newly set in the real address register (21).

Next, in step (26), the index array (5)
And the contents of the real address register (21)
(7) and the second comparator (8). It is checked whether or not one of the comparators matches, and it is detected whether or not the required data already exists in the cache array (6) (detection means). If it exists, go to step (23), and if it does not exist, go to step (27).

In step (27), the memory request issued in step (23) is continued as it is, and necessary data is taken out from the main storage device.

In step (28), the memory request issued in step (22) is aborted, and necessary data is fetched from the cache device (4).

As described above, when the information processing apparatus according to the present invention in FIG. 1 and the conventional information processing apparatus in FIG. 3 are compared,
When a plurality of cache devices are provided in the information processing device, it can be configured without holding the address translation device corresponding to each cache device. Therefore, according to the present invention, the information processing device has a smaller amount of hardware. There are advantages. Further, in terms of processing speed, comparing FIG. 2 with FIG. 4 shows that step (22), step (14), step (15), step (16) or step (17) in FIG. The processing time of the route that moves to is the same in the similar case in FIG. However, in FIG.
The processing time of the route going to step (22), step (23), step (24), step (25), step (26), step (28) is the same as that in this case in FIG. It takes longer than the processing time of the route to move to step (12), step (13), step (15), and step (17), but the difference is caused by aborting the memory request in step (28) in FIG. I am trying to reduce it.

In addition, in the above-described embodiment, the specific cache device having two columns has been described, but the same effect as that of the above-described embodiment can be obtained even if the cache device has another configuration.

〔The invention's effect〕

As described above, according to the present invention, since the cache device can be configured without holding the address translation device corresponding to each cache device, there is an effect that the hardware amount is reduced and the device can be inexpensive.

Further, the decrease in the processing speed when the configuration according to the present invention is adopted also depends on whether or not there is necessary data in the cache device after a valid real address value is set in the real address register after issuing a memory request. Since we decided to detect it, there is an effect that it can be suppressed to a minimum.

[Brief description of drawings]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a flowchart showing a series of operations of the information processing apparatus shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing the information processing apparatus, and FIG. 4 is a flowchart showing a series of operations of the conventional information processing apparatus shown in FIG. (1) is a memory address register, (4) is a cache device, (5) is an index array, (6) is a data array, (7) and (8) are comparators, (9) is a control circuit, and (10). Selector, (18) is address translation device, (19)
Is a detection control circuit, (20) is a valid instruction flag, and (21) is a real address register. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. An information processing apparatus having a plurality of buffer storage devices, wherein a copy of the contents of the main storage device is held so that data in the main storage device can be retrieved at high speed. Address conversion means for converting the logical address of the necessary data to be taken out from the main storage device into a real address, which is provided in a predetermined buffer storage device less than the number of A real address register provided in the address control unit of the storage device, which holds the result of address conversion by the address conversion means of the buffer storage device having the address conversion means, and a valid instruction flag of the real address register, The necessary data to be retrieved is stored in the buffer memory device that does not have the address conversion means. The information processing apparatus whether a decision to and performing with the real address register and a valid indication flag. 2. An information processing apparatus having a plurality of buffer storage devices, wherein a copy of the contents of the main storage device is held so that data in the main storage device can be extracted at high speed. Less than the number of predetermined buffer storage devices for converting logical addresses into real addresses, and the address control unit of the buffer storage device that does not have this address conversion means A real address register for holding the result of address translation by the address translation means of the buffer memory device having means, a valid indication flag of this real address register, an address boundary from which the current data is taken out, and an address boundary from which the previous data is taken out. And a request means for issuing a data retrieval request to the main storage device when Means for converting the logical address in which the necessary data exists into a real address by the address converting means, setting the real address in the real address register, and setting the valid instruction flag in the valid state; and the buffer memory device. Information comprising: detection means for detecting whether or not necessary data is present therein; and means for retrieving data from the buffer storage device by invalidating the data retrieval request when the data is present Processing equipment.