JPH0777077B2 - Memory circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit capable of time-divisionally reading or writing memory elements at a plurality of consecutive addresses from a designated address.

[Conventional technology]

2. Description of the Related Art In recent years, random access memory circuits using semiconductors have been proposed that have various functions as well as large memory capacities with the progress of integrated circuits. Among them, the information of the designated address is included only by continuously supplying a plurality of operation clocks to the memory circuit which can read or write only 1 bit of the information of the designated address, and a continuous plural number following this. A memory circuit has been proposed in which the information of the address can be read or written in a time division manner, and the memory circuit is operated efficiently.

This kind of conventional memory circuit has 8 rows x 8 rows as shown in FIG.
In the case of a matrix of 8 columns, a memory matrix 310 consisting of 64 memory elements arranged in a matrix of 8 rows × 8 columns, each of which is assigned addresses 0, 1, ..., 63, and arranged in the row direction of the matrix Eight row selection lines 420-427
And a row drive circuit 320 that selectively selects and drives these.
And 8 column information lines arranged in the column direction of the matrix
440 to 447 and the column writing circuit 34 which selectively selects them and executes write and read operations to them respectively.
0 and column read circuit 350, and address information 36 from the host device
Accumulate 5 and store these as row address line 361 and column address line
The address register 360 output to the 362 and the control information 375 from the host device are received, and the operation pulse is sent to the write / read controller 380.
Storage controller 370 for sending 371, and address register 360
The column address is received via the column address line 362 and stored therein, the column address is incremented by one each time the operation pulse 371 is received from the storage controller 370, and the result is stored in the column address lines 382a and 382b. A column read circuit 340 and a write / read control unit 380, which are provided to the column read circuit 350, respectively.

With respect to the above-mentioned conventional memory circuit, a read operation will be described with respect to the memory element at address 06 to continuous address 4 including this address as shown in the time chart of FIG. Note that the same operation is performed in the case of writing and can be easily inferred from the case of reading.

First, the row address “0” stored in the address register 360
And the column address “6” respectively via the row address line 361 and the column address line 362, the row drive circuit 320 and the write / read controller 380, respectively.
Given to. The row drive circuit 320 decodes the row address “0” and selects / drives the row selection line 420. The write / read control unit 380 stores the column address “6”, receives the operation clock 371 sent from the storage control unit 370, and supplies this column address “6” to the column read circuit 350 via the column address line 382b. . Thereafter, each time the operation clock 371 is received at a constant time interval t, the stored content is incremented by one, and the stored content "7""0""1" is transferred to the column read circuit 35 via the column address line 382b.
Give to 0. The column read circuit 350 sequentially decodes this column address and sequentially selects the column information lines 446, 447, 440, 441, and the address 6, 7, 0, 1 which is the intersection with the already selected row selection line.
The contents of the memory element are sequentially read and sent as read information 355 to the host device.

[Problems to be solved by the invention]

The conventional memory circuit described above is limited to reading and writing the memory element information from the same row selection line when continuously reading and writing data of a specific length from any address Reading / writing could not be performed across the memory element information of the select line. For this reason, it is a major drawback in practical use.

[Means for solving problems]

The memory circuit of the present invention has M (0, 1 ...
M-1) row selection lines and N (0,1) arranged in the column direction
... N-1) column information lines and memory elements arranged in a matrix of M rows x N columns (both are even numbers) at the intersections of the row selection lines and the column information lines, respectively, and the memory elements An address register for accumulating a register consisting of a row address and a column address designating one address of the address, an address decoder for decoding the row address and the column address respectively, and an output of the address decoder for selectively selecting the row selection line. A row drive circuit having a row drive selection circuit to be selected, a column write circuit having a write selection circuit for selectively providing write information to the column information line, and read information alternatively from the column information line And a column read circuit having a read selection circuit for reading the N column information lines, the N column information lines being the upper column information lines (0 to N / 2-1) and the lower information lines (N / 2 to N-).
1), the row selection line is divided into a first row selection line intersecting the upper column information line and a second row selection line intersecting the lower column information line, and the row driving circuit is divided into , A column address for selecting / driving the first row selection line and selecting an upper column between the address decoder and the row driving selection circuit, the output of the address decoder is given to the row driving selection circuit as it is. , A first row driving circuit having a rotate shift circuit for shifting the output of the address decoder to give the next row address to the row driving selecting circuit in the case of a column address for selecting a lower column, and the second row The selection line is divided into a second row drive circuit for selecting and driving, and
When the maximum address is selected, means to prohibit subsequent reading or writing and the operation to read or write by the signal that enables reading or writing of other memory circuits and the signal from other memory circuits And a circuit capable of reading and writing in a time-division manner the memory elements of a plurality of consecutive addresses from the address specified by the address across the row or across the storage circuit. Is.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, for simplicity, a case of a matrix of 8 rows × 8 columns will be described.

The memory circuit of FIG. 1 has a memory matrix 10 consisting of 64 memory elements arranged in a matrix of 8 rows × 8 columns and each of which is assigned addresses 0, 1 ..., 63. 10 is arranged in the column direction of the matrix 8
Connected to the column information lines 140 to 147. Column information line 140
˜147 select one of the column information lines as an alternative and write the write information 45 into the column write circuit 40, and select one of the column information lines as an alternative. It is connected to the column read circuit 50 from which the read information 55 is read. The column write circuit 40 and the column read circuit 50 are connected to the write / read control unit 80 via column address lines 82a and 82b, respectively.

Here, the eight column information lines 140 to 147 will be described in more detail. Each of these column information lines has four upper column information lines (140
To 143) and lower column information lines (144 to 147) and configured to be selected by the upper column selection address and the lower column selection address, respectively, the memory matrix 10 is further arranged in the row direction of the matrix. Eight first row selection lines 120-127 intersecting the upper column information lines 140-143 and eight second row selection lines 130-137 intersecting the lower column selection lines 144-147 It is connected to the. The first row selection lines 120 to 127 and the second row selection lines 130 to 137 selectively select and drive one of the first row driving line 20 and the second row selection line 130 to 137, respectively. It is connected to the drive circuit 30. The first row driving circuit 20 and the second row driving circuit 30 are connected to the address register 60 via the row address line 61. This address register receives and accumulates address information 65 consisting of a row address and a column address from a host device (not shown), and stores them respectively in a row address line.
61 and the column address line 62.

The storage control unit 70 receives the control information 75 including the write / read control signal and the operation clock from the upper device, and the row drive control unit 2
4, It is configured so that control signals, operation clocks, etc. can be sent to the write / read control unit 80, the row drive circuit 24 and the like. The write / read control unit 80 is configured to input an operation clock from the column address line 62 from the address register 60 and the storage control unit 70 via the control signal 71, and output it to the column address lines 82a and 82b. . The row drive controller 24 is configured to input a control signal from the column address line 62 from the address register 60 and the storage controller 70 via the control signal line 72 to control the first row drive circuit 20. There is.

The row drive circuit 20 has an address decoder 21, a row drive selection circuit 22, and a rotate shift circuit 23 between them, and decodes the row address received from the address register 60 via the row address line 61. , And has a function of selectively selecting and driving one of the row selection lines 120 to 127. At the time of this selection, the ON / OFF of the rotate shift circuit 23 is controlled by the output of the row drive controller 24 which operates according to the column address on the column address line 62 of the address register 60 and the control signal 72 from the storage controller 70 If the column address is the upper column selection address, the rotate shift circuit 23 is turned off to select the row selection line corresponding to the decoded row address. If the column address is the lower column selection address, the rotation shift circuit 23 is selected. Is turned on to select the row select line corresponding to the row address next to the decoded row address (the row next to row address 7 returns to row address 0).

The row drive circuit 30 includes an address decoder 31 and a row drive selection circuit 32.
And decodes the row address received from the address register 60 via the row address line 61, and selects the row selection lines 130 to 1
It has the function of selectively selecting and driving one of the 37.

The column write circuit 40 includes an address decoder 41 and a write selection circuit 42.
The column address received from the write / read control unit 80 via the column address line 82a is decoded, and the column information lines 140 to 1
One of 47 is selectively selected, and the selected column information line and the row selection line 120 selected by the row driving circuit 20 or 30, respectively.
1 to 127 or one of 130 to 137, it has a function of writing the write information 45 received from the host device.

The column read circuit 50 has an address decoder 51 and a read selection circuit 52, decodes the column address received from the write / read control unit 80 via the column address line 82, and selects one of the column information lines 140 to 147. One of the selected column information lines and the row selection line selected by the row drive circuit 20 or 30 respectively.
It has a function of reading information from a memory element at an intersection with one of 120 to 127 or one of 130 to 137 and sending the read information 55 to a higher-level device.

The write / read control unit 80 receives a column address from the address register 60 via the column address line 61 and stores the column address, and stores this column each time the operation clock is given from the storage control unit 70 via the control signal line 71. It has a function of incrementing the address by one (note that the column address is returned to the column address 0 after the column address 7), and the result is sent to the column write circuit 40 and the column read circuit 50 via the column address lines 82a and 82b. Address information provided by each
The memory elements at a plurality of consecutive addresses starting from the address specified by the 65 column addresses can be written or read in a time division manner.

The adjacent circuit control unit 90 receives the address signal 93 from the address register 60, and executes the adjacent circuit control signal 94 every time the storage control unit 70 executes a write or read operation for a plurality of consecutive addresses. It is compared whether the address is the maximum address, and if it is the maximum address, the memory control unit 70 is made to prohibit the subsequent write or read operation by the operation control signal 92 which prohibits the operation thereafter, and the adjacent circuit is activated. The output signal 91 is turned on after the maximum address. The adjacent circuit start-up input signal 95 is connected to the adjacent circuit start-up output signal of the adjacent memory circuit, and when it is turned on, the operation control signal 92 controls the memory control unit 70 to execute the write or read operation. have.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. Regarding one embodiment of the present invention in FIG. 2, 06
The read operation for the memory elements at addresses 4 continuous from address 6 will be described. In the case of writing, the operation is exactly the same, and it can be easily inferred from the case of reading.

First, “06” is given to the address register 60 as the address information 65 from the host device and accumulated. The row address “0” is input to the row drive circuit 20 and the row drive circuit 30, respectively. In the row drive circuit 20, the row drive control unit 24 inputs the column address "6", decodes that this is a lower column selection address, and turns on the rotate shift circuit 23. As a result, the row drive selection circuit 22 selects and drives the row selection line 121 corresponding to the next row address "1". In the row drive circuit 30, the row drive selection circuit 32 selectively drives the row selection line 130.

When the operation clock C0 shown in FIG. 2 is given as one of the control information 75 to the storage control unit 70, the storage control unit 70 causes the writing / reading control unit 80 to read through the control signal 71 in response to the operation clock. To start the operation of. The write / read control unit 80 uses the column address “6” given in advance as the column address line 82b.
To the column read circuit 50, and according to the decoding result of the address decoder 51, the read selection circuit 52 supplies the column information line 146.
Is selected and the content of the memory element "6" is read as read information 55. When the next operation clock C1 is applied, the write / read control unit 80 repeats the above operation with "7", which is the stored column address added by 1, as a new column address, and the content of the memory element "7" is read. To be done. When the clock C2 is further applied, the above operation is repeated with the column address "0", and the contents of the address 8 which is the intersection of the column information line 140 and the row selection line 121 already selected and driven by the row driving circuit 20 It is read. Further, when the clock C3 is applied, the contents of address 9 are read out as described above.

FIG. 3 is a diagram showing a configuration example of a circuit for reading or writing information of consecutive addresses from any address across the memory circuits by using a plurality of memory circuits according to the present invention. The first to fourth storage circuits 200 to 203 in FIG. 3 are all the same as the storage circuits described in FIG. The signals A, DI, DO, AI, AO in these memory circuits 200 to 203 are the address information 65, the write information 45, the read information 55, and the read information 55 in FIG.
It corresponds to the adjacent circuit activation input signal 95 and the adjacent circuit activation output signal 91, respectively. Note that E and C are the control information 75 in FIG. 1 and represent the enable signal and the clock signal, respectively.

In the embodiment shown in FIG. 3, four memory circuits 200-203 are combined to form a memory device having addresses 0-255, and the input / output signals of each memory circuit 200-203 are mutually connected. There is. The address is the first memory circuit by decoding the address 265 of each memory circuit 200 to 203 and the address of the higher 2 bits.
The first enable signal 270 of 200 to the fourth enable signal 273 of the fourth memory circuit 203 is sequentially added to the first to fourth memory circuits 200 to 203 to 0 to 63,64 to 127,128 to 191,
It is configured to be divided from addresses 192 to 255.

FIG. 4 is an explanatory diagram for reading address information continuously across the circuits in the embodiment of FIG. At the clock C0 of the operation of FIG. 4, the address of "62" is given and the "62" of the first memory circuit 200 of FIG. 3 is read. Similarly, at the operation clock C1, the address "63" of the first memory circuit 200 is read. With the operation clock C2, the first memory circuit 200
Since the maximum address is exceeded, the adjacent circuit activation output signal 91 in FIG. 1 is turned on, which turns on the adjacent circuit activation input signal (AI) of the second memory circuit 201 in FIG. The read operation of the circuit 201 is activated. At that time, the read operation is prohibited in the first memory circuit 200,
In the memory circuit 201 of, the address "64" is selected and "64" is selected.
The address information is read. Similarly, at the operation clock C3, the address "65" of the second memory circuit 201 is selected and the information at the address "65" is read.

In the above embodiment, the case where both the number of rows and the number of columns are 8 has been described, but the present invention is not limited to this, and both may be even numbers, and the total number of column information lines is N. ，
The first column information lines are 0, 1, ..., (N-1) / 2, for a total of N / 2 pieces, and the second column information lines are N / 2, (N + 1) / 2, ..., N-1. Total N
/ 2 pieces.

〔The invention's effect〕

As described above, according to the present invention, the row select line is divided into two, and the row shift circuit that drives one of the rows has a rotate shift circuit and the maximum address is detected to prohibit the subsequent operation and activate the adjacent circuit. By adding a function and reading / writing of memory elements at consecutive addresses from the specified address to the next row even between a plurality of memory circuits, a specific address can be specified from any address. There is an effect that it is possible to supply a memory circuit that makes it possible to continuously obtain length data with one command.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a time chart in an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention using a plurality of storage circuits. 4 is a block diagram showing a time chart in an embodiment of the present invention using a plurality of memory circuits, FIG. 5 is a block diagram showing a conventional memory circuit, and FIG. 6 is a conventional memory circuit. It is a figure which shows the time chart in a circuit. Explanation of symbols: 10 ... Memory matrix, 20,30 ... Row drive circuit, 21,31 ... Address decoder, 22,32 ... Row drive selection circuit, 23 ... Rotate shift circuit, 24 ... Row drive control Section 40 column write circuit 50 column read circuit 41 51 address decoder 42 write selection circuit 45 write information 52
...... Read selection circuit, 55 ...... Read information, 60 ...... Address register, 61 ...... Row address line, 62 ...... Column address line, 70 ......
Storage control unit, 71, 72 ... Control signal line, 75 ... Control information, 80 ...
... write / read controller, 82a, 82b ... column address line, 120 to 127,
130-137 …… Row selection line, 140-147 …… Column information line.

Claims (1)

[Claims] 1. M (0, 1, ..., M-1) arranged in the row direction
Row selection line and N (0, 1, ..., N−) arranged in the column direction
1) column information lines, memory elements arranged in a matrix of M rows and N columns (both are even numbers) at intersections of the row selection lines and column information lines, and one of the memory elements. An address register that stores an address consisting of a row address and a column address that specify an address, an address decoder that decodes the row address and the column address, and a row that selectively selects the row selection line by the output of the address decoder. A row drive circuit having a drive selection circuit,
A column write circuit having a write selection circuit for selectively providing write information to the column information line and a column read circuit having a read selection circuit for selectively reading read information from the column information line. In the storage circuit having the lower column information lines (N / 2 to N-1), the N column information lines are used as upper column information lines (0 to N / 2-1).
And dividing the row selection line into a first row selection line that intersects the upper column information line and a second row selection line that intersects the lower column information line, and the row drive circuit In the case of a column address that selects and drives the first row selection line and is between the address decoder and the row drive selection circuit, and in the case of a column address that selects an upper column, the output of the address decoder is given to the row drive selection circuit as it is In the case of a column address for selecting a lower column, a first row drive circuit having a rotate shift circuit that shifts the output of the address decoder to give the next row address to the row drive selection circuit, and the second row The selection line is divided into a second row drive circuit for selecting and driving, and further, when the maximum address is selected, means for prohibiting subsequent reading or writing and reading or writing for other memory circuits are performed. Possible And a signal from another storage circuit, which is a means for activating a read or write operation, and is a memory of a plurality of addresses continuous across a row from the address specified by the address or across the storage circuit. A memory circuit characterized in that an element can be read or written in a time division manner.