JPH0777342B2 - Composite semiconductor output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention is directed to an integrated circuit (hereinafter referred to as IC) such as Bi-CMOS in which bipolar transistors and MOSFETs are mixed on the same semiconductor substrate. Also referred to as a) composite type semiconductor output circuit.

(Prior Art) Bipolar transistor and MOSFET on the same semiconductor substrate
The Bi-CMOS IC in which the two are mixed has an advantage that the characteristics of both elements can be utilized to achieve high speed, large scale, and low power consumption.

As a conventional external power supply method in such a Bi-CMOS IC, a single kind of predetermined voltage is commonly supplied to its internal circuit and peripheral circuits via a stabilized power supply, and this predetermined voltage is supplied. Direct, bipolar transistor and MOSF
The method of applying to ET was taken. However, as the Bi-CMOS IC with such a configuration is further miniaturized in order to further increase the scale, etc., the breakdown voltage of the MOSFET decreases, greatly lowering the breakdown voltage of the bipolar transistor, and as a result, the power supply voltage is reduced. Will have to be lowered. But,
If the supply voltage drops below 5V, for example, other TTLI
It becomes impossible to secure a signal level with the C, CMOS IC, Bi-CMOS IC, etc., which leads to an increase in cost of a device using these ICs.

FIG. 5 shows the Bi-CM which has adopted the power supply method as described above.
The conventional example of the output circuit in OSIC is shown. In the figure,
1 is Bi-CM consisting of bipolar transistor and MOSFET
An internal circuit composed of OS etc., 2 is a pre-buffer circuit, and is a p-channel MOSFET (hereinafter referred to as pMOS etc.) M ₁
And a nMOSM ₂ CMOS inverter circuit. Further, 3 denotes a main buffer circuit consists of npn bipolar transistors _{Q 2, Q 3, pMOSM 23} , nMOSM 28, M 30, junction diode D _4, D ₅ and elements such as resistors R ₂ Bi-
It is composed of CMOS. 4 is an input terminal of the pre-buffer circuit 2, 5 is an input terminal of the main buffer circuit 3, 6 is an output terminal connected to the outside via the main buffer circuit 3,
Reference numeral 7 denotes a power supply terminal that supplies a single type of predetermined voltage from outside the IC chip to a output circuit including the internal circuit 1, the pre-buffer circuit 2 and the main buffer circuit 3 via a stabilizing power supply (not shown).

When a power supply voltage common to other ICs, such as 5V, is applied to the power supply terminal 7, its output, that is, the input terminal 4 of the prebuffer circuit 2 becomes H level due to the operation of the internal circuit 1. , Its potential V ₄ rises to 5V, and 5V is applied between the source and drain of pMOSM ₁ , between the gate and source of nMOSM ₂ , between the gate and source of pMOM ₂₃ , and between the gate and drain of nMOSM ₂₈ , and nMOSM ₃₀ Between the gate and drain of
A voltage of 4.3V is applied by subtracting 0.7V of the built-in voltage for one stage of diode D ₅ from V.

On the contrary, by the operation of the internal circuit 1, the input terminal 4
Goes to the L level and its potential V ₄ drops to the ground potential of 0 V, the gate-source and gate-source
A voltage of 5V to 4.3V is applied between the drains and between the source and the drain to perform the required operation as an output circuit.

(Problems to be solved by the invention) However, due to miniaturization of the constituent elements of the Bi-CMOS IC due to the increase in scale and the like, the gate breakdown voltage and drain breakdown voltage of the MOSFET are reduced, and these breakdown voltages are not When the voltage drops below a certain 5V, there is a problem that the MOSFET may break down or punch through to stop operating. Then, in order to avoid this gate destruction and punch through, when a voltage V ₇ lower than 5 V is supplied to the power supply terminal 7 to operate, the internal circuit 1 operates so that the input terminal 4 of the pre-buffer circuit 2 is at the H level. Then, the voltage V ₇ is applied to the base of the npn bipolar transistor Q ₂ which constitutes the main buffer circuit 3, and the emitter electrode, that is, the output terminal 6 connected to the outside of the IC concerned. , Npn Bipolar transistor Q ₂ built-in voltage V _T
A voltage (V ₇ −V _T ) reduced by (0.7V) is generated. Therefore, if another CMOS IC or Bi-CMOS IC that operates with a 5V power supply is connected to the next stage of this IC, this CMOS IC or Bi-CMOS IC
Input level decreases, the operating margin deteriorates and this CM
This leads to an increase in power consumption in OSIC or Bi-CMOS IC. In addition, to reduce the breakdown voltage of the MOSFET, the power supply voltage V ₇ is
For example, if it has to be lower than 2.7V, a voltage lower than about 2.0V will be generated at the output terminal 6, which will fall below the H level 2.0V of the TTLIC operation guarantee input.
There was a problem that direct connection with TTLIC could not be done.

Furthermore, since the power supply for the main buffer circuit connected to the final stage and requiring a large current drive and the power supply for the internal circuit are common, the power supply of the main buffer unit generated during the operation of the output circuit is There is a problem in that the noise induced on the power supply enters the internal circuit side and the operation of the internal circuit becomes unstable.

The present invention has been made based on the above circumstances, and even if the gate withstand voltage and the drain withstand voltage of the MOSFET are lowered due to the progress of miniaturization of the element, these low withstand voltage MOSFETs can be operated at a safe voltage equal to or lower than the withstand voltage. In addition, the signal level interface conditions with other CMOS ICs can be satisfied, and direct connection is possible without degrading the operation margin of these ICs. An object of the present invention is to provide a composite type semiconductor output circuit capable of stably operating an internal circuit without generating noise that is induced on the power supply of the main buffer unit to the internal circuit side.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides a composite semiconductor output circuit in an integrated circuit having bipolar transistors and MOSFETs formed on the same semiconductor substrate as constituent elements. A DC-DC converter for stepping down a first power supply voltage supplied from the outside to a second power supply voltage having a required voltage value, and an output signal from the internal circuit that operates together with an internal circuit at the second power supply voltage. , A signal level conversion circuit that operates at the first power supply voltage and level-converts an output signal from the internal circuit that is input via the pre-buffer circuit, and the signal level conversion circuit Means for pulling up and pulling down the binary level of the output signal to the outside by inputting the signal output from the first power supply voltage. And a level converting circuit and a pull-down means of the main buffer circuit, a MOSFET having a gate to which a bias voltage of a predetermined value is applied, and a logic MOSFET having an input signal to the gate. The gist of the present invention is that a pair transistor in which the two transistors are connected in series is used as a unit.

(Operation) Even if the gate withstand voltage and drain withstand voltage of the MOSFET are reduced in the above structure due to the progress of miniaturization of the device, these low withstand voltage MO
In the pre-buffer circuit and internal circuit that are composed of SFET, the first power supply voltage of the same voltage level as the power supply voltage of other CMOS ICs is stepped down by the DC-DC converter, and the low withstand voltage MOSF
The signal level conversion circuit, which is applied as a second power supply voltage having a safe voltage level equal to or lower than the withstand voltage of ET and operates at the first power supply voltage, has a gate having a predetermined bias voltage, for example, the second power supply. Bias voltage less than voltage is applied
It consists of a pair transistor in which two transistors, a MOSFET and a logic MOSFET to which an input signal is applied to the gate, are connected in series. Each MOSFET, like the pre-buffer circuit, has a safety level equal to or lower than the breakdown voltage of the low breakdown voltage MOSFET. Operates at various voltage levels. Further, the output signal from the internal circuit is level-converted by the signal level conversion circuit, and further, in the main buffer circuit, the H level and the L level of the output signal to the outside are pulled up and pulled down, respectively. Thus, the signal level interface condition with other CMOS ICs can be satisfied, and direct connection can be made without deteriorating the operation margin of these ICs. Further, the first power supply supplied to the main buffer circuit and the second power supply supplied to the internal circuit are separated from each other, and noise induced on the power supply of the main buffer section generated during the operation of the output circuit is internally generated. It is possible to prevent the power from flowing into the power supply of the circuit, and the internal circuit operates stably.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. Incidentally, FIG. 1 and FIGS. 2 to 4 showing each embodiment described later.
In the figure, the same or equivalent parts as the circuit devices, elements and the like in FIG. 5 are designated by the same reference numerals as those used above, and the duplicated description will be omitted.

First, the structure of the composite semiconductor output circuit will be described.
In the figure, 7 is a first power supply terminal to which a first power supply voltage V ₇ having a predetermined value is supplied from the outside through a stabilized power supply (not shown), 10 is a DC-DC converter, and 8 is a DC-DC converter. Is a second power supply terminal for generating a second power supply voltage V ₈ lower than the first power supply voltage V ₇ , and the second power supply terminal 8 is commonly connected to the internal circuit 1 and the pre-buffer circuit 20. There is.
The pre-buffer circuit 20 includes pMOS and nMOS, M ₁ and M ₂ , M ₃ and M ₄
, And each inverter circuit composed of M ₅ and M ₆ , respectively. Reference numeral 30 denotes a signal level conversion circuit, which includes three junction diodes D ₁ , D ₂ , D ₃ , a resistor R ₁ and a logic pMOSM ₇ , nMOSM ₁₀ for applying an input signal to the gate, and a bias of a predetermined value to the gate. PMOSM ₉ and nMOSM ₈ to which voltage is applied
It is composed of. A main buffer circuit 40 is an nMOSM in which a predetermined bias voltage is applied to a pull-up circuit 41 composed of an npn bipolar transistor Q ₁ as pull-up means and a gate as pull-down means.
_A pull-down circuit 42 including a logic nMOSM ₁₄ to which an input signal is applied to the gate ₁₂ is provided. The first power supply voltage V ₇ from the first power supply terminal ₇ is directly applied to the signal level conversion circuit 30 and the main buffer circuit 40 described above.

9 is the input signal terminal of the pull-up circuit, 11 is the input signal terminal of the pull-down circuit, 12, 13 and 14 are the internal terminals of the signal level conversion circuit, 15 is the gate bias application terminal of pMOSM ₉ , and 16 is
The gate bias application terminal of nMOSM ₈ , 17 is the gate bias application terminal of nMOSM ₁₂ , and 18 is the internal terminal of the pull-down circuit.

Next, the operation of the composite semiconductor output circuit configured as described above will be described.

By the operation of the internal circuit 1, when its output, that is, the input terminal 4 of the pre-buffer circuit becomes H level, its potential
V ₄ rises to the second power supply voltage V ₈ and the MOSFETs M ₁ , M ₄ , M ₆
Is non-conductive, M ₂ , M ₃ , and M ₅ are conductive, and the potentials V ₅ and V 11 of the input signal terminals 5 and ₁₁ are up to the second power supply voltage V ₈ supplied to the pre-buffer circuit 20. To rise. Therefore, nMOSM ₁₀ connected to input signal terminal 5 and other input signal terminals 1
The nMOSM ₁₄ connected to 1 becomes conductive.

In addition, the potential V ₁₂ of the internal terminal 12 in the signal level conversion circuit 30
If V _D is the built-in voltage of each diode D ₁ , D ₂ , and D ₃ , it will not conduct unless V ₁₂ V ₈ + 3V _D or more. Now, if V ₈ = 3V and V _D = 0.7V, V _{12 It} does not conduct unless it is 5.1V. Here, the first power supply terminal 7 has an affinity with other ICs (mainly TTLIC),
For example, since a 5V power supply is used, after all, diode D ₁ ,
D ₂ and D ₃ become non-conducting and the internal terminal 12 potential V ₁₂ = V
Increases to ₇ (5V). Therefore, pMOSM ₇ becomes non-conductive.

Here, with the threshold voltage of the pMOS being Vthp, a constant bias voltage V ₁₅ of V ₈ − | Vthp | or less is applied to the gate bias application terminal 15, and the same constant bias voltage as V ₈ is applied to the other gate bias application terminals 16. When V ₁₆ is applied, the nMOSM ₈ and M ₁₀ become conductive, the potential V ₁₃ of the internal terminal 13 changes to V ₁₅ + | Vthp | = V ₈ , the pMOSM ₉ becomes non-conductive, and the nMOSM ₈ , M ₁₀
Is conductive, the input signal terminal 9 of the pull-up circuit eventually drops to the ground potential, and the npn bipolar transistor Q ₁ becomes non-conductive.

On the other hand, the gate bias application terminal 17 of the input signal terminal 11 and the NMOSM ₁₂ of the pull-down circuit is in the potential of the second power supply voltage V _8, because both nMOSM _12, M ₁₄ is in a conducting state, the external output terminal 6 Pulled down to ground potential 0V.

Since the above operation is performed, the direct current path from the first and second power supply terminals 7 and 8 to the ground is cut off,
Moreover, the gate-source voltage, the gate-drain voltage, the gate-back gate voltage, and the source-drain voltage higher than the second power supply voltage V ₈ are not applied to all the MOSFETs.

Next, conversely to the above, when the signal output from the internal circuit 1 becomes L level, V ₄ = 0V, and each input signal terminal 5,
The potentials of ₁₁ turn to V ₅ = V ₁₁ = 0V, respectively. At this time, the diodes D ₁ , D ₂ and D ₃ become conductive, and the internal terminals
12 is three stages of the diode built-in voltage V _D , that is, V
_It drops to ₁₂ = 3V _D and pMOSM ₇ becomes conductive.

On the other hand, the nMOSM ₁₀ becomes non-conductive, and the nMOS threshold voltage is set to V
Since th _{17 is} V ₁₇ = V ₈ , the internal terminal 14 is V ₈ −Vt
It rises to hn and nMOSM ₈ becomes non-conductive. And pMOSM ₇
Is conductive, the internal terminal 13 rises to V ₇ , and V ₁₅ = V ₈ − | Vthp | <V ₇ , so pMOSM ₉ is conductive and the input signal terminal 9 of the pull-up circuit is It rises to the first power supply voltage V ₇ .
Further, since V ₁₁ = 0V, the nMOM ₁₄ is in a non-conducting state, and since the internal terminal 18 is V ₁₇ = V ₈ , it rises to V ₈ −Vthn and the nMOSM ₁₂ becomes non-conducting.

Therefore, the base current from the first power supply terminal 7 is made conductive is supplied to the npn bipolar transistor Q _1, the emitter potential of the npn bipolar transistors Q _1, i.e., the potential of the external output terminal 6, between the forward base-emitter Voltage to V _BE
Is pulled up to V ₇ −V _BE .

Since such operation, the use of of a sufficiently high resistance value to the resistor R _1, the first power supply terminal 7, R _1, D _1, D _2,
The DC current flowing through D ₃ and M ₄ can be suppressed to a sufficiently small level, and the source-drain voltage of nMOSM ₈ is V ₇
−V ₈ + Vthn, which is smaller than V _{8 in} the range of 2V ₈ −V ₇ + Vthn 0, and the source-drain voltage of nMOSM ₁₂ is V ₇ −V _BE −V ₈ + Vthn, which is 2V ₈ −V ₇ Less than V _{8 in} the range of + V _BE + Vthn0, typically V ₇ = 5V, V ₈ = 3V
About Vthn = V _BE = 0.7V, so all M
No gate-source voltage, gate-drain voltage, gate-back gate voltage, source-drain voltage higher than the second power supply voltage V ₈ is applied to the OSFET.

Further, the voltage V ₆ of the output terminal 6 is independent of V ₈ from a V ₆ = V ₇ -V _BE, the V ₈ for lowering of the MOSFET breakdown voltage
The output voltage of this output circuit does not decrease even when the voltage is lower than V ₇ . As is clear from this result, the effect is that the level of the output signal output to the outside of the IC with low power consumption can be made the same condition as the signal level of other Bi-CMOS ICs. At the same time, it is possible to guarantee the high reliability and high performance of all MOSFETs that make up this IC.

Next, FIG. 2 shows a second embodiment of the present invention. In FIG. 2, 21 is a pre-buffer circuit, 31 is a signal level conversion circuit, and this signal level conversion circuit 31 has pMOS M ₁₅ , M ₁₇ , M ₂₁ , and nMO in which a bias voltage of a predetermined value is applied to the gate.
SM ₁₆ , M ₁₈ , M ₂₄ and pMOS for logic M ₁₁ , M ₁₃ , M ₁₉ , nMOS
It is composed of M ₂₀ , M ₂₂ , and M ₂₆ .

24, 25, 26 are input signal terminals of the signal level conversion circuit, 27,
28, 29, 32, 33, 34, 35, 36 are internal terminals of the signal level conversion circuit, 37 is a gate bias application terminal of pMOS M ₁₅ , M ₁₇ .
38 is the gate bias application terminal of pMOSM ₂₁ , 39 is nMOSM ₁₆ ,
M _{18 is} a gate bias application terminal, and 43 is an nMOS M ₂₄ gate bias application terminal.

Since the composite semiconductor output circuit of this embodiment is configured as described above, the signal output from the internal circuit 1 is L
At the level, if the potential is 0 V, the MOSFETs in the pre-buffer circuit 21 have M ₁ , M ₄ , and M ₅ conducting, and M ₂ , M ₃ and M ₆
There becomes non-conductive, the potential V ₁₁ of the voltage V _26, 11 of the potential V _24, 26 of the potential V _25, 24 of the input signal terminal 25, respectively V ₂₅ =
V ₈ and V ₂₄ = V ₂₆ = V ₁₁ = 0V.

Therefore, nMOSM ₂₂ becomes conductive, M ₂₀ becomes nonconductive, and the internal terminal
The potential V ₃₅ of ₃₅ becomes 0V, and the threshold voltage of the pMOS is set to Vthp, and V ₈ − | Vthp | is applied to the gate bias application terminals 37 and 38, and V is applied to 39 and 43, as in the case of the first embodiment. _When a voltage of ₈ is applied, the nMOSM ₂₄ becomes conductive and the potential V ₃₃ of the internal terminal 33 becomes 0V. At this time, the potential V ₂₇ of the internal terminal _{27, V 27> V 37 + |} Vthp | a long if PMOSM _{17 conducts, V 27 = V 37 + |} Vthp | = potential to V ₈ drops. Since V ₈ <V ₇ , pMOSM ₁₁ becomes conductive, the potential V ₂₈ of the internal terminal 28 rises to V ₇ , and pMOSM ₁₃ becomes nonconductive. Also, pMOSM ₁₅ is conducting and internal terminal 3
The potential V ₃₂ of 2 is clamped by V ₃₉ , the threshold voltage of the nMOS is set to Vthn, and the potential is raised to V ₃₉ = V ₈ −Vthn, and the nMOS M ₁₆ becomes non-conductive.

The operations of the MOSFETs M ₁₉ , M ₂₁ , M ₂₄ , and M ₂₆ are the same as those in the first embodiment. In this embodiment, V ₂₇ = V ₈ , so that M ₁₉ conducts and the input a M ₂₆ because the potential V ₂₄ = 0V signal terminal 24 is non-conductive, the potential V ₉ of the input signal terminal 9 of the pull-up circuit is increased to V _7, npn bipolar transistor Q from the first power supply terminal 7 A base current of ₁ is supplied and it becomes conductive.

The operation of the main buffer circuit 40 is similar to that of the first embodiment. In this case, since the npn bipolar transistor Q ₁ is conductive and V ₁₁ = 0V, M ₁₄ is nonconductive and the potential of the external output terminal 6 is V ₆ is pulled up the threshold voltage of the npn bipolar transistor Q ₁ to V ₇ -V _bE as V _bE.

Since it operates in this way, the direct current path from both power supply terminals 7 and 8 to ground is cut off, and all MOSFETs are cut off.
As in the case of the first embodiment, no gate-source voltage, gate-drain voltage, gate-back gate voltage, source-drain voltage higher than V ₈ is applied. Furthermore, since V ₆ = V ₇ −V _BE , the MOSFE
Even if V ₈ is lowered below V ₇ for the purpose of lowering the T breakdown voltage, the output voltage of this output circuit does not lower as in the case of the first embodiment.

Next, when the signal output from the internal circuit 1 changes to H level and V ₄ = V ₈ , the potential of each input signal terminal becomes V ₂₅ = 0.
V and V ₂₄ = V ₂₆ = V ₁₁ = V ₈ . Signal level conversion circuit 31
Has a symmetric configuration with respect to M ₁₃ , M ₁₇ , M ₂₄ , M ₂₂ and M ₁₁ , M ₁₅ , M ₁₆ , M ₂₀ , resulting in a symmetric operation to the above case, and V ₂₈ = V ₈ and V ₂₇ = V ₇ . At this time, M ₁₉ becomes non-conductive and V ₂₆ = V ₈ , so that M ₂₆ becomes conductive and V ₉ = 0V.
Becomes

Therefore, the npn bipolar transistor Q ₁ becomes non-conductive, and since V ₁₁ = V ₈ , M ₁₄ becomes conductive and the potential V ₆ of the external output terminal ₆ is pulled down to the ground potential 0V.

Since it operates in this way, in this case as well, both power supply terminals 7 and 8
DC current path to ground from being cut off, and all of the MOSFET, if a high gate-source voltage than V ₈ in the same manner described above, the gate-drain voltage, the gate-back gate voltage, the source -No drain-to-drain voltage is applied. As is clear from this result, as its effect, the power consumption is further reduced as compared with the first embodiment, and the output signal level to be output to the outside of the IC is set to other Bi-
Under the same conditions as the signal level of CMOS IC,
The high reliability and high performance of the MOSFETs that make up the device are guaranteed.

It is also possible to easily realize an output circuit having a tri-state function composed of NAND gates, NOR gates, etc. in the pre-buffer circuit.

FIG. 3 shows a third embodiment having this tri-state function. In this embodiment, a tristate function is added to the prebuffer circuit in the output circuit of the first embodiment. In FIG. 3, 45 and 46 are CMOS or Bi-
Inverter gate of CMOS configuration, G ₁ and G ₄ are CMOS
Alternatively, a 2-input NAND gate having a Bi-CMOS configuration, a 2-input NOR gate, and 44 are control input terminals of the prebuffer circuit 22.

When an H level potential V ₄₄ is applied to this control input terminal 44,
The potential of the input signal terminal 5 of the signal level conversion circuit is V ₈ , V ₁₁
= 0V, pMOSM ₇ (see Figure 1) is non-conductive, nMOSM ₁₀ is conductive, and V ₉ = 0V. Therefore, since V ₁₁ = 0V, both the npn bipolar transistors Q ₁ and M ₁₄ become non-conductive, and the output is in a high impedance state.
On the other hand, when the control input terminal 44 is 0V at the L level, the prebuffer circuit 22 operates in the same manner as in the case of the first embodiment.

Next, FIG. 4 shows a fourth embodiment in which a tri-state function is added to the pre-buffer circuit in the output circuit of the second embodiment.
An example is shown. In the figure, 47, 48, 49, and 51 in the pre-buffer circuit 23 are inverter gates of CMOS or Bi-CMOS configuration, and G ₂ and G ₃ are two inputs of CMOS or Bi-CMOS configuration.
It is a NAND gate.

In this embodiment, as in the case of the third embodiment, when an H level potential V ₈ is applied to the control input terminal 44, V ₂₅ = V ₁₁ = 0
Since V and V ₂₄ = V ₂₆ = V ₈ , V ₂₇ (see FIG. 2) = V ₇ ,
M ₂₆ is conductive, V ₉ = 0V, npn bipolar transistor
Since Q ₁ is non-conducting and V ₁₁ = 0V, M ₁₄ is non-conducting,
The output is in a high impedance state. On the other hand, if the control input terminal 44 is 0V at the L level, the prebuffer circuit 23 operates similarly to the case of the second embodiment.

In each of the above embodiments, the main buffer circuit 40
When the emitter follower Darlington connection configuration is used exclusively for the TTL interface in the pull-up circuit 41 in FIG. 1, when the emitter follower + diode one-stage cascade connection configuration is used, and the pull-down circuit 42 is configured by a grounded-emitter circuit using a bipolar transistor. In each case, it is clear that the same effects as the effects of the above-described embodiments are obtained. Further, in each of the embodiments, even if the second power supply voltage V ₈ is directly supplied from the outside to the second power supply terminal 8 without passing through the DC-DC converter 10, the operational effect described in each of the embodiments is obtained. It is clear to have

[Effects of the Invention] As described above, according to the present invention, the DC-DC converter for stepping down the first power supply voltage supplied from the outside to the second power supply voltage of the required voltage value is provided, and the internal circuit is provided. A pre-buffer circuit that operates at the second power supply voltage is connected to the next stage together with the internal circuit, and a signal level conversion circuit that operates at the first power supply voltage is connected to the next stage of the pre-buffer circuit. , The final stage is provided with means for inputting a signal output from the signal level conversion circuit and pulling up and pulling down a binary level of an output signal to the outside, respectively, and operating with the first power supply voltage. The level conversion circuit and the pull-down means of the main buffer circuit have a buffer circuit, and the level conversion circuit and the pull-down means of the main buffer circuit are a MOSFET whose gate is applied with a bias voltage of a predetermined value and a logic MOSFE whose gate is applied with an input signal. Since a pair transistor in which two transistors of T and T are connected in series is used as a unit, even if miniaturization of the device progresses and the gate breakdown voltage and drain breakdown voltage of the MOSFET decrease, a pre-buffer composed of these low breakdown voltage MOSFETs It is possible to operate circuits and internal circuits with a safe power supply voltage that is lower than the withstand voltage lower than the power supply voltage of other CMOS ICs and Bi-CMOS ICs. Further, similarly to the above, it is composed of a low withstand voltage MOSFET, and operates at the first power supply voltage to increase the drive capability of the main buffer circuit of the next stage, and outputs the output signal level up to the first power supply voltage operation level. The signal level conversion circuit for raising the voltage and the pull-down means in the main buffer circuit, which also operates at the first power supply voltage, are configured with a pair of transistors as a unit, so that each MOSFET has a safe voltage equal to or lower than the withstand voltage, as described above. Can be operated at a level. Therefore, the reliability of ultra-small, low-voltage MOSFETs is guaranteed and their use is possible.
It is possible to achieve large scale, high speed and low power consumption of CMOS ICs, and also to use other CMOS ICs, Bi-CMOS ICs, or TTs.
There is an advantage that the signal level interface condition with LIC can be satisfied and direct connection can be made without degrading the operation margin of these ICs.

Further, since the first power supply connected to the final stage and supplied to the main buffer circuit that needs to drive a large current is separated from the second power supply supplied to the internal circuit, the output There is an advantage in that the noise induced on the power supply of the main buffer section generated during the operation of the circuit does not flow into the power supply of the internal circuit, and the internal circuit operates stably.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a composite semiconductor output circuit according to the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention, and FIG.
The figure is a circuit diagram of a conventional composite type semiconductor output circuit. 1: internal circuit, 6: output terminal, 7: first power supply terminal, 8: second power supply terminal, 10: DC-DC converter, 20, 21, 22, 23: pre-buffer circuit, 30, 31: signal Level conversion circuit, 40: Main buffer circuit, 41: Pull-up circuit (pull-up means), 42: Pull-down circuit (pull-down means), M ₁ ~
M ₂₈ : MOSFET, Q ₁ : npn bipolar transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuji Horiguchi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) References JP 62-21323 (JP, A)

Claims (1)

[Claims] 1. A composite semiconductor output circuit in an integrated circuit comprising a bipolar transistor and a MOSFET formed on the same semiconductor substrate as constituent elements, wherein a first power supply voltage supplied from the outside is a second of a required voltage value.
A DC-DC converter for stepping down to the power supply voltage, a pre-buffer circuit that operates together with an internal circuit at the second power supply voltage and receives an output signal from the internal circuit, and a pre-buffer circuit that operates at the first power supply voltage. A signal level conversion circuit for converting the level of the output signal from the internal circuit input via the pre-buffer circuit, and a binary level of the output signal to the outside by inputting the signal output from the signal level conversion circuit And a main buffer circuit which is provided with means for pulling up and pulling down, respectively, and which operates at the first power supply voltage, and the signal level conversion circuit and the pull-down means of the main buffer circuit are configured to bias the gate with a predetermined value. A pair transistor in which two transistors, a MOSFET to which a voltage is applied and a logic MOSFET to which an input signal is applied to the gate, are connected in series A composite semiconductor output circuit characterized by being configured as follows.